MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 399

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2.2
Read and write anytime
Freescale Semiconductor
IBC[7:0]
Reset
Field
7:0
W
R
IBC7
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
IIC Frequency Divider Register (IBFD)
0
7
Table
9-3.
IBC5-3
(bin)
000
001
010
011
100
101
110
111
IBC6
= Unimplemented or Reserved
0
6
Figure 9-4. IIC Bus Frequency Divider Register (IBFD)
Table 9-3. I-Bus Tap and Prescale Values
scl2start
(clocks)
IBC2-0
(bin)
Table 9-2. IBFD Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
000
001
010
011
100
101
110
111
126
14
30
62
IBC5
2
2
2
6
0
5
IBC4
scl2stop
SCL Tap
(clocks)
(clocks)
0
4
129
10
12
15
17
33
65
5
6
7
8
9
7
7
9
9
Description
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
IBC3
0
3
SDA Tap
(clocks)
(clocks)
scl2tap
126
14
30
62
1
1
2
2
3
3
4
4
4
4
6
6
IBC2
0
2
(clocks)
tap2tap
128
16
32
64
1
2
4
8
IBC1
0
1
IBC0
0
0
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