C8051F061-GQR Silicon Laboratories Inc, C8051F061-GQR Datasheet - Page 14

• Manufacturer Part Number: C8051F061-GQR
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F061-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F060/1/2/3/4/5/6/7
22. UART0.................................................................................................................... 265
23. UART1.................................................................................................................... 277
24. Timers.................................................................................................................... 287
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Figure 21.1. SPI Block Diagram ............................................................................. 251
Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 254
Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Figure 21.5. Master Mode Data/Clock Timing ........................................................ 256
Figure 21.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 257
Figure 21.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 257
Figure 21.8. SPI0CFG: SPI0 Configuration Register ............................................. 258
Figure 21.9. SPI0CN: SPI0 Control Register.......................................................... 259
Figure 21.10. SPI0CKR: SPI0 Clock Rate Register ............................................... 260
Figure 21.11. SPI0DAT: SPI0 Data Register.......................................................... 261
Figure 21.12. SPI Master Timing (CKPHA = 0)...................................................... 262
Figure 21.13. SPI Master Timing (CKPHA = 1)...................................................... 262
Figure 21.14. SPI Slave Timing (CKPHA = 0)........................................................ 263
Figure 21.15. SPI Slave Timing (CKPHA = 1)........................................................ 263
Figure 22.1. UART0 Block Diagram ....................................................................... 265
Figure 22.2. UART0 Mode 0 Timing Diagram ........................................................ 267
Figure 22.3. UART0 Mode 0 Interconnect.............................................................. 267
Figure 22.4. UART0 Mode 1 Timing Diagram ........................................................ 267
Figure 22.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 269
Figure 22.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 270
Figure 22.7. UART Multi-Processor Mode Interconnect Diagram .......................... 272
Figure 22.8. SCON0: UART0 Control Register ...................................................... 274
Figure 22.9. SSTA0: UART0 Status and Clock Selection Register........................ 275
Figure 22.10. SBUF0: UART0 Data Buffer Register .............................................. 276
Figure 22.11. SADDR0: UART0 Slave Address Register ...................................... 276
Figure 22.12. SADEN0: UART0 Slave Address Enable Register .......................... 276
Figure 23.1. UART1 Block Diagram ....................................................................... 277
Figure 23.2. UART1 Baud Rate Logic .................................................................... 278
Figure 23.3. UART Interconnect Diagram .............................................................. 279
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 279
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 280
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 281
Figure 23.7. SCON1: Serial Port 1 Control Register .............................................. 282
Figure 23.8. SBUF1: Serial (UART1) Port Data Buffer Register ............................ 283
Figure 24.1. T0 Mode 0 Block Diagram.................................................................. 288
Figure 24.2. T0 Mode 2 Block Diagram.................................................................. 289
Figure 24.3. T0 Mode 3 Block Diagram.................................................................. 290
Figure 24.4. TCON: Timer Control Register ........................................................... 291
Figure 24.5. TMOD: Timer Mode Register ............................................................. 292
254
254
Rev. 1.2