C8051F061-GQR Silicon Laboratories Inc, C8051F061-GQR Datasheet - Page 52

• Manufacturer Part Number: C8051F061-GQR
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F061-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F060/1/2/3/4/5/6/7
5.1.
ADC0 and ADC1 can be programmed to operate independently as single-ended ADCs, or together to
accept a differential input. In single-ended mode, the ADCs can be configured to sample simultaneously, or
to use different conversion speeds. In differential mode, ADC1 is a slave to ADC0, and its configuration is
based on ADC0 settings, except during offset or gain calibrations. The DIFFSEL bit in the Channel Select
Register AMX0SL (Figure 5.6) selects between single-ended and differential mode.
5.1.1. Pseudo-Differential Inputs
The inputs to the ADCs are pseudo-differential. The actual voltage measured by each ADC is equal to the
voltage between the AINn pin and the AINnG pin. AINnG must be a DC signal between -0.2 and 0.6 V. In
most systems, AINnG will be connected to AGND. If not tied to AGND, the AINnG signal can be used to
negate a limited amount of fixed offset, but it is recommended that the internal offset calibration features of
the device be used for this purpose. When operating in differential mode, AIN0G and AIN1G should be tied
together. AINn must remain above AINnG in both modes for accurate conversion results.
52
AIN0G
AIN1G
AIN0
AIN1
Interface
Single-Ended or Differential Operation
DMA
Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram
ADC0
ADC1
16-Bit
16-Bit
SAR
SAR
ADC0GTH
ADC1H
16
16
8
16
8
ADC0GTL
ADC1L
Rev. 1.2
+
-

1
0
AMX0SL
Single-Ended
Differential
ADC0LTH
ADC0H
8
16
ADC0LTL
8
ADC0L
Compare
Window
32
AD0WINT