C8051F061-GQR Silicon Laboratories Inc, C8051F061-GQR Datasheet - Page 230

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C8051F061-GQR

Manufacturer Part Number
C8051F061-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Datasheets

Specifications of C8051F061-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
C8051F061-GQR
Manufacturer:
SILICON
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Part Number:
C8051F061-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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C8051F060/1/2/3/4/5/6/7
230
CAN Register
Index
0x0C
0x0D
0x0A
0x0B
0x0E
0x0F
0x2A
0x04
0x05
0x06
0x08
0x09
0x10
0x11
0x12
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x40
0x41
0x48
0x49
0x50
0x51
0x58
BRP Extension Register
Transmission Request 1
Transmission Request 2
IF1 Command Request
IF2 Command Request
IF1 Message Control
IF2 Message Control
IF1 Command Mask
IF2 Command Mask
Interrupt Pending 1
Interrupt Pending 2
Table 19.1. CAN Register Index and Reset Values (Continued)
Interrupt Register
Message Valid 1
IF1 Arbitration 1
IF1 Arbitration 2
IF2 Arbitration 1
IF2 Arbitration 2
Register name
Test Register
IF1 Data A1
IF1 Data A2
IF1 Data B1
IF1 Data B2
IF2 Data A1
IF2 Data A2
IF2 Data B1
IF2 Data B2
New Data 1
New Data 2
IF1 Mask 1
IF1 Mask 2
IF2 Mask 1
IF2 Mask 2
0xFFFF CAN0ADR autoincrement upon write to CAN0DATL
0xFFFF CAN0ADR autoincrement upon write to CAN0DATL
0xFFFF CAN0ADR autoincrement upon write to CAN0DATL
0xFFFF CAN0ADR autoincrement upon write to CAN0DATL
0x0000 Read Only
0x0000 Bit 7 (RX) is determined by CAN bus
0x0000 Write Enabled by TEST bit in CAN0CN
0x0001 CAN0ADR autoincrements in IF1 index space (0x08
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0001 CAN0ADR autoincrements in IF1 index space (0x08
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 CAN0ADR autoincrement upon write to CAN0DATL
0x0000 Transmission request flags for message objects
0x0000 Transmission request flags for message objects
0x0000 New Data flags for message objects (read only)
0x0000 New Data flags for message objects (read only)
0x0000 Interrupt pending flags for message objects (read
0x0000 Interrupt pending flags for message objects (read
0x0000 Message valid flags for message objects (read only)
Reset
Value
Rev. 1.2
- 0x12) upon write to CAN0DATL
- 0x12) upon write to CAN0DATL
(read only)
(read only)
only)
only)
Notes

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