HD64F3687FPIV Renesas Electronics America, HD64F3687FPIV Datasheet - Page 219

MCU 3/5V 56K I-TEMP PB-FREE 64-L

HD64F3687FPIV

Manufacturer Part Number
HD64F3687FPIV
Description
MCU 3/5V 56K I-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3687FPIV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3687FPIV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
13.3.4
TFCR selects the settings and output levels for each operating mode.
Bit
7
6
5
4
3
2
Bit Name
STCLK
ADEG
ADTRG
OLS1
OLS0
Timer Function Control Register (TFCR)
Initial
Value
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 1.
External Clock Input Select
0: External clock input is disabled
1: External clock input is enabled
A/D Trigger Edge Select
A/D module should be set to start an A/D conversion by
the external trigger
0: A/D trigger at the crest in complementary PWM mode
1: A/D trigger at the trough in complementary PWM mode
External Trigger Disable
0: A/D trigger for PWM cycles is disabled in
1: A/D trigger for PWM cycles is enabled in
Output Level Select 1
Selects the counter-phase output levels in reset
synchronous PWM mode or complementary PWM mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
Output Level Select 0
Selects the normal-phase output levels in reset
synchronous PWM mode or complementary PWM mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
Figure 13.4 shows an example of outputs in reset
synchronous PWM mode and complementary PWM
mode when OLS1 = 0 and OLS0 = 0.
complementary PWM mode
complementary PWM mode
Rev.5.00 Nov. 02, 2005 Page 185 of 500
Section 13 Timer Z
REJ09B0027-0500

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