HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 139

MCU 5V 32K PB-FREE 64-DIP

HD6473258P10V

Manufacturer Part Number
HD6473258P10V
Description
MCU 5V 32K PB-FREE 64-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheets

Specifications of HD6473258P10V

Core Size
8-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Operating Temperature
-20°C ~ 75°C
Package / Case
64-DIP
No. Of I/o's
53
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
3
Digital Ic Case Style
DIP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/330
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
600
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
1 200
Part Number:
HD6473258P10V
Manufacturer:
HITACHI/日立
Quantity:
20 000
Bit 7
ICF
0
1
Bit 6 – Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches
the OCRB value.
This flag must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Bit 6
OCFB
0
1
Bit 5 – Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches
the OCRA value.
This flag must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Bit 5
OCFA
0
1
Bit 4 – Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes
from H’FFFF to H’0000).
This flag must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Description
To clear ICF, the CPU must read ICF after it
has been set to 1, then write a 0 in this bit.
This bit is set to 1 when an FTI input signal causes the FRC
value to be copied to the ICR.
Description
To clear OCFB, the CPU must read OCFB after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when FRC = OCRB.
Description
To clear OCFA, the CPU must read OCFA after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when FRC = OCRA.
131
(Initial value)
(Initial value)
(Initial value)

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