HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 83

• Manufacturer Part Number: HD6473258P10V
• Description: MCU 5V 32K PB-FREE 64-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10V

• Core Size: 8-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• No. Of I/o's: 53
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Digital Ic Case Style: DIP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/330
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt request
signal
Internal Read
signal
Internal Write
signal
Internal 16-bit
data bus
Ø
Internal address
bus
(1)
(2) (4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
(1)
(2) (4) Instruction code (Not executed)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
CCR
interrupt-handling routine.)
SP–2
SP–4
Address of vector table entry
Vector table entry (address of first instruction interrupt-handling routine)
First instruction of interrupt-handling routine
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
Instruction prefetch address (Not executed)
Interrupt priority
decision. Wait for
end of instruction.
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
interrupt-handling routine.)
Instruction code (Not executed)
Instruction prefetch address (Not executed)
SP–2
SP–4
CCR
Address of vector table entry
Vector table entry (address of first instruction interrupt-handling routine)
First instruction of interrupt-handling routine
(1)
(2)
Interrupt
accepted
Figure 4-6. Timing of Interrupt Sequence
Instruction
fetch
(3)
(4)
Internal
process-
ing
74
(5)
(1)
Stack
(6)
(7)
Vector
table
fetch
(8)
(9)
Internal
process-
ing
Figure. 4-6
Instruction fetch
(first instruction of
interrupt-handling
routine)
(9)
(10)