SAF-TC1164-128F80HL AB Infineon Technologies, SAF-TC1164-128F80HL AB Datasheet - Page 33

• Manufacturer Part Number: SAF-TC1164-128F80HL AB
• Description: IC MCU 32BIT FLASH LQFP176-2
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1164-128F80HL AB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 76K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 36x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 76.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Preliminary
3.3.2
The bus-specific address maps describe how the different bus master devices react on
accesses to on-chip memories and modules, and which address ranges are valid or
invalid for the corresponding buses.
The FPI Bus address map shows the system addresses from the point of view of the
SPB master agents. SPB master agents are PCP2 and OCDS, and DMA.
The LMB address map shows the system addresses from the point of view of the LMB
master agents. LMB master agents are PMI and DMI.
Table 3-2
(Table 3-3
Table 3-2
Term
…BE
…BET
SPBBE
SPBBET
LMBBE
LMBBET
access
ignore
trap
32
nE
Data Sheet
defines the acronyms and other terms that are used in the address maps
to
How to Read the Address Maps
Table
Definition of Acronyms and Terms
3-5).
Description
Means “Bus error” generation.
Means “Bus error & trap” generation.
A bus access is terminated with a bus error on the SPB.
A bus access is terminated with a bus error on the SPB and a DSE
trap (read access) or DAE trap (write access).
A bus access is terminated with a bus error on the LMB.
A bus access is terminated with a bus error on the LMB and a DSE
trap (read access) or DAE trap (write access).
A bus access is allowed and is executed.
A bus access is ignored and is not executed. No bus error is
generated.
A DSE trap (read access) or DAE trap (write access) is generated.
Only 32-bit word bus accesses are permitted to that
register/address range.
A bus access generates no bus error, although the bus access
points to an undefined address or address range. This is valid e.g.
for CPU accesses (MTCR/MFCR) to undefined addresses in the
CSFR range.
29
Functional Description
TC1163/TC1164
V1.0, 2008-04