SAF-TC1164-128F80HL AB Infineon Technologies, SAF-TC1164-128F80HL AB Datasheet - Page 78

• Manufacturer Part Number: SAF-TC1164-128F80HL AB
• Description: IC MCU 32BIT FLASH LQFP176-2
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1164-128F80HL AB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 76K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 36x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 76.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Preliminary
3.17
The WDT provides a highly reliable and secure way to detect and recover from software
or hardware failure. The WDT helps to abort an accidental malfunction of the
TC1163/TC1164 in a user-specified time period. When enabled, the WDT will cause the
TC1163/TC1164 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1163/TC1164 system reset. Hence, routine service
of the WDT confirms that the system is functioning as expected.
In addition to this standard “Watchdog” function, the WDT incorporates the End-of-
Initialization (Endinit) feature and monitors its modifications. A system-wide line is
connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection). Registers protected via this line
can only be modified when Supervisor Mode is active and bit ENDINIT = 0.
A further enhancement in the TC1163/TC1164’s WDT is its reset prewarning operation.
Instead of resetting the device upon the detection of an error immediately (the way that
standard Watchdogs do), the WDT first issues a Non-Maskable Interrupt (NMI) to the
CPU before resetting the device at a specified time period later. This step gives the CPU
a chance to save the system state to the memory for later investigation of the cause of
the malfunction; an important aid in debugging.
Features
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Data Sheet
16-bit Watchdog counter
Selectable input frequency:
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated Password Access mechanism with fixed and user-definable password
fields
Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and is limited.
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1163/TC1164 is held in reset until a power-on or
hardware reset occurs. This prevents the device from being periodically reset if, for
instance, connection to the external memory has been lost such that system
initialization could not even be performed.
Watchdog Timer
f
SYS
/256 or
74
f
SYS
/16384
Functional Description
TC1163/TC1164
V1.0, 2008-04