SAF-C167CS-L16M 3V CA+ Infineon Technologies, SAF-C167CS-L16M 3V CA+ Datasheet - Page 69

• Manufacturer Part Number: SAF-C167CS-L16M 3V CA+
• Description: IC MCU 16BIT ROM/LESS MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C167CS-L16M 3V CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 11 KB
• Interface Type: ASC, CAN, SSC
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 16.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: F167CSL16M3VCAZNT; F167CSL16M3VCAZXT; SAFC167CSL16M3VCAT; SP000017109; SP000103470

interdependencies between certain parameters. Some of these interdependencies are
described as relative timing (see below) or in additional notes (see standard timing).
Table 18
Parameter
Output hold time after WR rising edge
Valid for: address, write data out
Input hold time after RD rising edge
Valid for: read data in
1)
2)
General Notes For The Following Bus Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1)
2)
3)
4)
Data Sheet
Not 100% tested, guaranteed by design and characterization.
See also note
The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit
BUSCON.RWDCx).
The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx).
A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.
A bus cycle is extended here, if an MTTC waitstate is selected.
2)
External Bus Relative Timing (Operating Conditions apply)
in
Table
17.
2)
65
Symbol
t
t
50
51
CC 0
SR –
min.
C167CS-L16M3V
Limits
max.
–
0
Low Power
V1.0, 2001-10
1)
Unit
ns
ns