AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 56

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADC Control and Status Register - ADCSR
•
Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while
a conversion is in progress, will terminate this conversion.
•
In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Run Mode, a logical ‘1’
must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been
enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated con-
version. This dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the conversion is complete, but before the result is written
to the ADC Data Registers. This allows a new conversion to be initiated before the current conversion is complete. The new
conversion will then start immediately after the current conversion completes. When a dummy conversion precedes a real
conversion, ADSC will stay high until the real conversion completes.
Writing a 0 to this bit has no effect.
•
When this bit is set (one) the ADC operates in Free Run Mode. In this mode, the ADC samples and updates the data regis-
ters continuously. Clearing this bit (zero) will terminate Free Run Mode.
•
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Com-
plete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if
doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
•
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
•
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
Table 22. ADC Prescaler Selections
56
Bit
$06 ($26)
Read/Write
Initial value
Bit 7 - ADEN: ADC Enable
Bit 6 - ADSC: ADC Start Conversion
Bit 5 - ADFR: ADC Free Run Select
Bit 4 - ADIF: ADC Interrupt Flag
Bit 3 - ADIE: ADC Interrupt Enable
Bits 2..0 - ADPS2..ADPS0: ADC Prescaler Select Bits
ADPS2
AT90S/LS2333 and AT90S/LS4433
0
0
0
0
1
1
1
1
ADEN
R/W
7
0
ADSC
R/W
6
0
ADPS1
ADFR
R/W
0
0
1
1
0
0
1
1
5
0
ADIF
R/W
4
0
ADIE
R/W
3
0
ADPS0
0
1
0
1
0
1
0
1
ADPS2
R/W
2
0
ADPS1
R/W
1
0
ADPS0
R/W
0
0
Division Factor
ADCSR
128
16
32
64
2
2
4
8