PIC17C42A-33I/PQ Microchip Technology, PIC17C42A-33I/PQ Datasheet
PIC17C42A-33I/PQ
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PIC17C42A-33I/PQ Summary of contents
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... High-Performance 8-Bit CMOS EPROM/ROM Microcontroller Devices included in this data sheet: • PIC17CR42 • PIC17C42A • PIC17C43 • PIC17CR43 • PIC17C44 • PIC17C42† Microcontroller Core Features: • Only 58 single word instructions to learn • All single cycle instructions (121 ns) except for program branches and table reads/writes which are two-cycle • ...
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... DS30412C-page 2 MQFP TQFP RD4/AD12 39 RD5/AD13 38 37 RD6/AD14 36 RD7/AD15 TEST MCLR/V 35 RE2/WR PP RE1/ RE0/ALE RE0/ALE RE1/OE MCLR RE2/WR RD7/AD15 TEST 29 RD6/AD14 RD5/AD13 RD4/AD12 RB4/TCLK12 1 33 RB3/PWM2 RB2/PWM1 4 30 RB1/CAP2 5 29 RB0/CAP1 RC7/AD7 9 25 RC6/AD6 10 24 RC5/AD5 RC4/AD4 11 23 1996 Microchip Technology Inc. ...
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... We appreciate your assistance in making this a better document. To assist you in the use of this document, Appendix C contains a list of new information in this data sheet, while Appendix D contains information that has changed 1996 Microchip Technology Inc. To Our Valued Customers PIC17C4X ...
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... PIC17C4X NOTES: DS30412C-page 4 1996 Microchip Technology Inc. ...
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... OVERVIEW This data sheet covers the PIC17C4X group of the PIC17CXX family of microcontrollers. The following devices are discussed in this data sheet: • PIC17C42 • PIC17CR42 • PIC17C42A • PIC17C43 • PIC17CR43 • PIC17C44 The PIC17CR42, PIC17C42A, PIC17CR43, and PIC17C44 devices include architec- tural enhancements over the PIC17C42 ...
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... Program Memory Code Protect I/O Pins I/O High Current Capabil- Source 25 mA ity Sink 25 mA Package Types 40-pin DIP 44-pin PLCC 44-pin MQFP Note 1: Pins RA2 and RA3 can sink mA. DS30412C-page 6 PIC17CR42 PIC17C42A 33 MHz 33 MHz 2.5 - 6.0V 2 232 232 232 - Yes ...
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... EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before produc- tion shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP ...
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... PIC17C4X NOTES: DS30412C-page 8 1996 Microchip Technology Inc. ...
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... MHz), except for program branches and two special instructions that transfer data between program and data memory. The PIC17C4X can address up to 64K program memory space. The PIC17C42 and PIC17C42A integrate EPROM program memory on-chip, PIC17CR42 has ROM program memory on- chip ...
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... PIC17C4X FIGURE 3-1: PIC17C42 BLOCK DIAGRAM DS30412C-page 10 <8> BUS DATA 1996 Microchip Technology Inc. ...
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... FIGURE 3-2: PIC17CR42/42A/43/R43/44 BLOCK DIAGRAM 1996 Microchip Technology Inc. PIC17C4X <8> BUS DATA DS30412C-page 11 ...
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... This is also the lower half of the 16-bit wide system bus in microprocessor mode or extended microcontroller I/O TTL mode. In multiplexed system bus configuration, these I/O TTL pins are address output as well as data input or output. I/O TTL I/O TTL I/O TTL I/O TTL I/O TTL ) input. PP 1996 Microchip Technology Inc. ...
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... 16 Legend Input only Output only; I/O = Input/Output Power; — = Not Used; TTL = TTL input Schmitt Trigger input. 1996 Microchip Technology Inc. I/O/P Buffer Description Type Type PORTD is a bi-directional I/O Port. I/O TTL This is also the upper byte of the 16-bit system bus in ...
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... Q4 (destination write PC+1 Fetch INST (PC+1) Execute INST (PC) Tcy1 Tcy2 Tcy3 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal phase clock PC+2 Fetch INST (PC+2) Execute INST (PC+1) Tcy4 Tcy5 Flush Fetch SUB_1 Execute SUB_1 1996 Microchip Technology Inc. ...
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... PWRT On-chip 10-bit Ripple counter RC OSC† † This RC oscillator is shared with the WDT when not in a power-up sequence. 1996 Microchip Technology Inc. This document was created with FrameMaker PIC17C4X Power-on Reset (POR), Power-up 4.1 Timer (PWRT), and Oscillator Start-up Timer (OST) 4 ...
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... SLEEP Greater of: 1024T — OSC 1024T OSC Greater of: — — 1024T OSC STATUS BITS AND THEIR SIGNIFICANCE Event > PWRT OST CPUSTA OST Active Yes --11 11-- No --11 11-- (2) --11 10-- Yes No --11 01-- (2) --11 00-- Yes (2) --11 10-- Yes (2) --10 10-- Yes 1996 Microchip Technology Inc. ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1996 Microchip Technology Inc. T PWRT T OST T PWRT T OST ) PWRT T OST ...
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... PIC17C42 EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW V DD POWER-UP MCLR PIC17C42 C power-up time is too DD powers DD pin is 5 A). A larger PP level on the IH pin. PP pin PP BROWN-OUT PROTECTION CIRCUIT MCLR 40 k PIC17CXX is below 0.7V V • 1996 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt vector. 3: See Table 4-3 for reset value of specific condition. 4: Only applies to the PIC17C42. 5: Does not apply to the PIC17C42. 1996 Microchip Technology Inc. MCLR Reset Power-on Reset WDT Reset 0000 0000 ...
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... Wake-up from SLEEP through interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- ---- uu-- ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1996 Microchip Technology Inc. ...
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... TXIF TXIE RCIF RCIE RBIF RBIE 1996 Microchip Technology Inc. This document was created with FrameMaker PIC17C4X When an interrupt is responded to, the GLINTD bit is automatically set to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with the interrupt vector address. There are four interrupt vectors. Each vector address is for a specifi ...
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... When disabling any of the INTSTA enable bits, the GLINTD bit should be set (disabled). PEIE T0CKIE T0IE INTE bit0 R = Readable bit W = Writable bit - n = Value at POR reset 1996 Microchip Technology Inc. ...
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... TXIE : USART Transmit Interrupt Enable bit 1 = Enable Transmit buffer empty interrupt 0 = Disable Transmit buffer empty interrupt bit 0: RCIE : USART Receive Interrupt Enable bit 1 = Enable Receive buffer full interrupt 0 = Disable Receive buffer full interrupt 1996 Microchip Technology Inc. CA1IE TXIE RCIE R = Readable bit W = Writable bit bit0 ...
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... Before enabling an interrupt, the user may wish to clear the interrupt flag to ensure that the program does not immedi- ately branch to the peripheral interrupt ser- vice routine CA2IF CA1IF TXIF RCIF R = Readable bit W = Writable bit bit0 -n = Value at POR reset 1996 Microchip Technology Inc. ...
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... External Interrupt on T0CKI (T0CKIF) 0020h Peripherals (PEIF) 1996 Microchip Technology Inc. Note 1: Individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the GLINTD bit. Note 2: When disabling any of the INTSTA enable bits, the GLINTD bit should be set (disabled) ...
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... PIE register. Some of the peripheral interrupts can wake the processor from SLEEP. See Section 14.4 for details on SLEEP opera- tion Addr (Vector) Inst (Vector) Addr Inst (PC+1) Addr Addr RETFIE Dummy Dummy Inst ( Addr Dummy RETFIE 1996 Microchip Technology Inc. ...
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... MOVFP TEMP_STATUS, ALUSTA MOVFP TEMP_BSR, BSR RETFIE 1996 Microchip Technology Inc. Example 5-1 shows the saving and restoring of infor- mation for an interrupt service routine. The PUSH and POP routines could either be in each interrupt service routine or could be subroutines that were called. ...
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... PIC17C4X NOTES: DS30412C-page 28 1996 Microchip Technology Inc. ...
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... FF60h Boot ROM FFFFh Note 1: User memory space may be internal, external, or both. The memory configuration depends on the processor mode. 2: This location is reserved on the PIC17C42. DS30412C-page 29 0000h 0008h 0010h 0018h 0020h 0021h 7FFh (PIC17C42, PIC17CR42, PIC17C42A) FFFh (PIC17C43 PIC17CR43) 1FFFh (PIC17C44) ...
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... No Access No Access Microcontroller Access Extended Access No Access Microcontroller Protected Access Microcontroller FIGURE 6-2: MEMORY MAP IN DIFFERENT MODES Microprocessor Mode PIC17C42, 0000h PIC17CR42, PIC17C42A External Program Memory FFFFh OFF-CHIP 00h FFh OFF-CHIP PIC17C43, 0000h PIC17CR43, PIC17C44 External Program Memory FFFFh OFF-CHIP 00h ...
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... WR Note 1: Use of I/O pins is only required for paged memory. 2: This signal is unused for ROM and EPROM devices. 1996 Microchip Technology Inc. In extended microcontroller mode, when the device is executing out of internal memory, the control signals will continue to be active. That is, they indicate the action that is occurring in the internal memory ...
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... The peripheral registers are in the banked portion of memory, while the core registers are in the unbanked region. To facilitate switching between the peripheral banks, the MOVLB bank instruction has been provided. 1996 Microchip Technology Inc. ...
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... General 20h Purpose RAM FFh Note 1: SFR file locations 10h - 17h are banked. All other SFRs ignore the Bank Select Register (BSR) bits. 1996 Microchip Technology Inc. FIGURE 6-6: Addr Unbanked 00h INDF0 01h FSR0 02h PCL 03h PCLATH ...
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... RC1/ RC0/ xxxx xxxx uuuu uuuu AD1 AD0 1111 1111 1111 1111 RD1/ RD0/ xxxx xxxx uuuu uuuu AD9 AD8 ---- -111 ---- -111 RE0/ALE ---- -xxx ---- -uuu TXIF RCIF 0000 0010 0000 0010 TXIE RCIE 0000 0000 0000 0000 1996 Microchip Technology Inc. ...
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... All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000) except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu) 5: The PRODL and PRODH registers are not implemented on the PIC17C42. 1996 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... WREG register or a file register. For two operand instructions, one of the operands is the WREG register and the other one is either a file register or an 8-bit immediate constant bit0 R = Readable bit W = Writable bit -n = Value at POR reset (x = unknown) 1996 Microchip Technology Inc. ...
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... Enables all un-masked interrupts bit 3: TO: WDT Time-out Status bit 1 = After power- CLRWDT instruction Watchdog Timer time-out occurred bit 2: PD: Power-down Status bit 1 = After power- the CLRWDT instruction execution of the SLEEP instruction bit 1-0: Unimplemented: Read as '0' 1996 Microchip Technology Inc — — bit0 ...
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... Unimplemented: Read as '0' DS30412C-page PS2 PS1 PS0 — bit0 ) Readable bit W = Writable bit U = Unimplemented, reads as ‘0’ Value at POR reset 1996 Microchip Technology Inc. ...
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... After the device is “PUSHed” sixteen times (without a “POP”), the seventeenth push overwrites the value from the first push. The eighteenth push overwrites the second push (and so on). 1996 Microchip Technology Inc. PIC17C4X 6.4 Indirect Addressing Indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not fi ...
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... The table latch is used as a temporary holding latch during data transfer between program and data memory (see descriptions of instructions TABLRD, TABLWT, TLRD and TLWT). For a more complete description of these registers and the operation of Table Reads and Table Writes, see Section 7.0. 1996 Microchip Technology Inc. ...
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... PCLATH PCLATH PCL PCH 1996 Microchip Technology Inc. Using Figure 6-11, the operations of the PC and PCLATH for different instructions are as follows: a) LCALL instructions: An 8-bit destination address is provided in the instruction (opcode). PCLATH is unchanged. PCLATH PCH Opcode<7:0> b) Read instructions on PCL: Any instruction that reads PCL. ...
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... In the PIC17CR42, and PIC17C42A only the lower nibble is implemented. While in the PIC17C43, PIC17CR43, and PIC17C44 devices, the entire byte is implemented. The lower nibble is used to select the peripheral regis- ter bank. The upper nibble is used to select the general purpose memory bank ...
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... TLWT 0,f DATA MEMORY PROGRAM MEMORY f 1 Note 1: 8-bit value, from register 'f', loaded into the high or low byte in TABLAT (16-bit). 1996 Microchip Technology Inc. This document was created with FrameMaker PIC17C4X FIGURE 7-2: TABLWT INSTRUCTION OPERATION TABLE POINTER TBLPTRH TBLPTRL TABLE LATCH (16-bit) ...
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... Program Memory (TBLPTR) loaded into TABLAT register “i” then TBLPTR = TBLPTR + 1, If “i” then TBLPTR is unchanged. TABLRD INSTRUCTION OPERATION TBLPTRL TABLATL 3 TABLRD 0,i,f PROGRAM MEMORY Prog-Mem (TBLPTR) 2 1996 Microchip Technology Inc. ...
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... Peripheral 1996 Microchip Technology Inc. 7.1.1 TERMINATING LONG WRITES An interrupt source or reset are the only events that terminate a long write operation. Terminating the long write from an interrupt source requires that the inter- rupt enable and flag bits are set. The GLINTD bit only enables the vectoring to the interrupt address ...
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... Flag bit, Do table write. The highest pending interrupt is cleared. for the next write. In TABLE WRITE ; Clear WDT ; address ; ; ; Load HI byte ; in TABLATCH ; Load LO byte ; in TABLATCH ; and write to ; program memory ; (Ext. SRAM Data out PC+2 INST (PC+2) INST (PC+1) 1996 Microchip Technology Inc. ...
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... Instruction TABLWT1 TABLWT2 fetched Instruction TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2 INST (PC-1) executed ALE OE WR 1996 Microchip Technology Inc. TBL1 Data out 1 PC+2 TBL2 INST (PC+2) Data write cycle Data write cycle PIC17C4X Data out 2 PC+3 INST (PC+3) ...
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... Data read cycle TBL1 Data in 1 PC+2 TBL2 Data in 2 INST (PC+2) Data read cycle Data read cycle ; address ; ; ; Dummy read, ; Updates TABLATCH ; Read HI byte ; of TABLATCH ; Read LO byte ; of TABLATCH and ; Update TABLATCH PC+2 PC+3 INST (PC+3) INST (PC+2) 1996 Microchip Technology Inc. ...
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... All other PIC17CXX devices signed PIC17C42 All other PIC17CXX devices 1996 Microchip Technology Inc. This document was created with FrameMaker Example 8-2 shows the sequence signed multiply. To account for the sign bits of the arguments, each argument’s most significant bit (MSb) is tested and the appropriate subtractions are done ...
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... ARG1H, WREG ; MULWF ARG2L MOVFP PRODL, WREG ; ADDWF RES1, F MOVFP PRODH, WREG ; ADDWFC RES2, F CLRF WREG, F ADDWFC RES3 MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; Add cross products ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; Add cross products ; ; ; 1996 Microchip Technology Inc. ...
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... MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L 16 = (ARG1H * ARG2H * (ARG1H * ARG2L * (ARG1L * ARG2H * 2 ) (ARG1L * ARG2L) (-1 * ARG2H<7> * ARG1H:ARG1L * 2 (-1 * ARG1H<7> * ARG2H:ARG2L * 2 1996 Microchip Technology Inc. EXAMPLE 8-4: MOVFP ARG1L, WREG MULWF ARG2L MOVPF PRODH, RES1 ; MOVPF PRODL, RES0 ; ; MOVFP ARG1H, WREG MULWF ARG2H MOVPF PRODH, RES3 ...
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... PIC17C4X NOTES: DS30412C-page 52 1996 Microchip Technology Inc. ...
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... Note: A pin that is a peripheral input, can be con- figured as an output (DDRx<y> is cleared). The peripheral events will be determined by the action output on the port pin. 1996 Microchip Technology Inc. This document was created with FrameMaker PIC17C4X PORTA Register 9.1 PORTA is a 6-bit wide latch. PORTA does not have a corresponding Data Direction Register (DDR) ...
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... Serial port input signal Data Bus RD_PORTA (Q2) Serial port output signals and Value on Value on all Bit 0 Power-on other resets Reset (Note1) RA0/INT 0-xx xxxx 0-uu uuuu — 0000 000- 0000 000- RC9D 0000 -00x 0000 -00u TX9D 0000 --1x 0000 --1u 1996 Microchip Technology Inc. ...
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... Weak Pull-Up OE Note: I/O pins have protection diodes to V and V DD 1996 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the inter- rupt by: a) Read-Write PORTB (such as; MOVPF PORTB, PORTB ). This will end mismatch condition. ...
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... BLOCK DIAGRAM OF RB3 AND RB2 PORT PINS Weak Pull-Up OE Note: I/O pins have protection diodes to V and Vss. DD DS30412C-page 56 Match Signal from other port pins Port Input Latch D Port Q Data CK Peripheral Data in (PORTA<7>) RBPU RBIF Data Bus RD_DDRB (Q2) RD_PORTB (Q2 WR_DDRB (Q4 WR_PORTB (Q4) PWM_output PWM_select 1996 Microchip Technology Inc. ...
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... CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON Legend unknown unchanged unimplemented read as '0 Value depends on condition. Shaded cells are not used by PORTB. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 1996 Microchip Technology Inc. EXAMPLE 9-1: MOVLB 0 CLRF ...
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... Initialize PORTC data ; latches before setting ; the data direction ; register ; Value used to initialize ; data direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs to D_Bus IR INSTRUCTION READ Data Bus RD_PORTC WR_PORTC RD_DDRC WR_DDRC EX_EN DATA/ADDR_OUT SYS BUS Control DRV_SYS 1996 Microchip Technology Inc. ...
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... DDRC Data direction register for PORTC Legend unknown unchanged. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 1996 Microchip Technology Inc. Function Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. ...
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... Initialize PORTD data ; latches before setting ; the data direction ; register ; Value used to initialize ; data direction ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs to D_Bus IR INSTRUCTION READ Data Bus RD_PORTD WR_PORTD RD_DDRD WR_DDRD EX_EN DATA/ADDR_OUT SYS BUS Control DRV_SYS 1996 Microchip Technology Inc. ...
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... DDRD Data direction register for PORTD Legend unknown unchanged. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 1996 Microchip Technology Inc. Function Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. ...
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... Initialize PORTE data ; latches before setting ; the data direction ; register ; Value used to initialize ; data direction ; Set RE<1:0> as inputs ; RE<2> as outputs ; RE<7:3> are always ; read as '0' Data Bus RD_PORTE WR_PORTE RD_DDRE WR_DDRE EX_EN CNTL SYS BUS Control DRV_SYS 1996 Microchip Technology Inc. ...
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... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 1996 Microchip Technology Inc. Function Input/Output or system bus Address Latch Enable (ALE) control pin. ...
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... Port pin sampled here MOVF PORTB,W NOP PORTB<3:0> Outputs PORT latch PORT pins ---------- --------- 01pp pppp 11pp pppp 10pp pppp 11pp pppp 10pp pppp 11pp pppp 10pp pppp 10pp pppp - instruction cycle propagation delay PD 1996 Microchip Technology Inc. ...
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... When the TMR2:TMR1 value rolls over from the period match value to 0h, the TMR1IF flag is set, and an interrupt will be generated when enabled. 1996 Microchip Technology Inc. This document was created with FrameMaker PIC17C4X 10.3 Timer2 Overview The TMR2 module is an 8-bit timer/counter with an 8- bit period register (PR2) ...
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... PIC17C4X NOTES: DS30412C-page 66 1996 Microchip Technology Inc. ...
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... Unimplemented : Read as '0' 1996 Microchip Technology Inc. This document was created with FrameMaker PS2 PS1 PS0 — bit0 ) CY PIC17C4X R = Readable bit W = Writable bit U = Unimplemented, ...
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... Prescaler (8 stage Synchronization async ripple PSOUT counter PS3:PS0 (T0STA<4:1>) (note PSOUT is sampled here. with the internal phase clocks. and 7T . Thus, for example, mea- OSC ( 121 MHz). OSC Interrupt on overflow sets T0IF (INTSTA<5>) TMR0H<8> TMR0L<8> (note 3) (note 1996 Microchip Technology Inc. ...
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... Fetch MOVFP W,TMR0L Instruction Write to TMR0L executed TMR0H 1996 Microchip Technology Inc. 11.3.2 WRITING A 16-BIT VALUE TO TMR0 Since writing to either TMR0L or TMR0H will effectively inhibit increment of that half of the TMR0 in the next cycle (following write), but not inhibit increment of the other half, the user must write to TMR0L first and TMR0H next in two consecutive instructions, as shown in Example 11-2 ...
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... Read TMR0L Read TMR0L Value on Value on all Bit 1 Bit 0 Power-on other resets Reset (Note1) PS0 — 0000 000- 0000 000- — — --11 11-- --11 qq-- T0IE INTE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
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... TMR1CS : Timer1 Clock Source Select bit 1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin 0 = TMR1 increments off the internal clock 1996 Microchip Technology Inc. This document was created with FrameMaker Timer3 is a 16-bit timer/counter consisting of the TMR3H and TMR3L registers. This timer has four other associated registers ...
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... TMR1ON : Timer1 On bit When T16 is set (in 16-bit Timer Mode Starts 16-bit Timer2:Timer1 0 = Stops 16-bit Timer2:Timer1 When T16 is clear (in 8-bit Timer Mode Starts 8-bit Timer1 0 = Stops 8-bit Timer1 DS30412C-page bit0 R = Readable bit W = Writable bit -n = Value at POR reset 1996 Microchip Technology Inc. ...
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... RB4/TCLK12 1 Fosc/4 0 TMR2CS (TCON1<1>) 1996 Microchip Technology Inc. 12.1.1.1 EXTERNAL CLOCK INPUT FOR TIMER1 OR TIMER2 When TMRxCS is set, the clock source is the RB4/TCLK12 pin, and the timer will increment on every falling edge on the RB4/TCLK12 pin. The TCLK12 input is synchronized with internal phase clocks. This causes a delay from the time a falling edge appears on TCLK12 to the time TMR1 or TMR2 is actually incremented ...
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... RCIE 0000 0000 0000 0000 INTE 0000 0000 0000 0000 — --11 11-- --11 qq-- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — xx-- ---- uu-- ---- — xx0- ---- uu0- ---- DC2 xxxx xxxx uuuu uuuu DC2 xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
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... If the new duty cycle is written after the timer has passed that value, then the PWM does not reset at all during the current cycle causing a “glitch”. In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10. 1996 Microchip Technology Inc. FIGURE 12-5: SIMPLIFIED PWM BLOCK Duty Cycle registers ...
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... PWM, its frequency should be much less than the device frequency (Fosc). PWM FREQUENCY vs. RESOLUTION AT 25 MHz Frequency (kHz) 48.8 65.104 97.66 390.6 0x7F 0x5F 0x3F 0x0F 9-bit 8.5-bit 8-bit 6-bit 7-bit 6.5-bit 6-bit 4-bit CY , unless the external clock is syn- CY 1996 Microchip Technology Inc. ...
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... DC8 Legend unknown unchanged unimplemented read as '0 value depends on conditions, shaded cells are not used by PWM. 1996 Microchip Technology Inc. Timer3 has two modes of operation, depending on the CA1/PR3 bit (TCON2<3>). These modes are: • One capture and one period register mode • ...
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... PR3H/CA1H PR3L/CA1L Comparator<8> Comparator x16 Equal Reset TMR3H TMR3L Capture1 Enable CA2H CA2L flag bits is shown in ;Select Bank 3 ;Read Capture2 low ;byte, store in LO_BYTE ;Read Capture2 high ;byte, store in HI_BYTE ;STAT_VAL Set TMR3IF (PIR<6>) Set CA2IF (PIR<3>) 1996 Microchip Technology Inc. ...
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... Capture. Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset. 1996 Microchip Technology Inc. The Capture2 overflow status flag bit is double buff- ered. The master bit is set if one captured word is already residing in the Capture2 register and another “ ...
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... Write to TMRx Read TMRx Read TMRx indicates a sampling point. to timer increment is between 2Tosc and 6Tosc. TMR3L ; TMR3H ; ;read low tmr0 ;read high tmr0 ;tmplo wreg ;tmr0l < wreg? ;no then return ;read low tmr0 ;read high tmr0 ;return 00h 'A9h' 1996 Microchip Technology Inc. ...
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... Bank 3 CA2H Capture2 high byte Legend unknown unchanged unimplemented read as '0', shaded cells are not used by TMR1, TMR2 or TMR3. Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset. 1996 Microchip Technology Inc. BSF BCF 3 NOP MOVLB ...
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... PIC17C4X NOTES: DS30412C-page 82 1996 Microchip Technology Inc. ...
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... TSR empty 0 = TSR full bit 0: TX9D : 9th bit of transmit data (can be used to calculated the parity in software) 1996 Microchip Technology Inc. This document was created with FrameMaker The SPEN (RCSTA<7>) bit has to be set in order to configure RA4 and RA5 as the Serial Communication Interface ...
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... OERR : Overrun Error bit 1 = Overrun (Cleared by clearing CREN overrun error bit 0: RX9D : 9th bit of receive data (can be the software calculated parity bit) DS30412C-page — FERR OERR RX9D bit Readable bit W = Writable bit -n = Value at POR reset (x = unknown) 1996 Microchip Technology Inc. ...
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... FIGURE 13-3: USART TRANSMIT Sync/Async CK/TX Start TXREG FIGURE 13-4: USART RECEIVE OSC 4 BRG Master/Slave Buffer Logic CK SPEN Buffer Logic RX 1996 Microchip Technology Inc. BRG Sync/Async Sync/Async TSR Clock 7 8 Stop Load 8 Bit Count TXSTA<0> Data Bus TXIE Sync/Async Sync Bit Count ...
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... CREN — FERR OERR TXEN SYNC — — TRMT RATE ERROR 16000000 /( 1)) 25.042 = 25 Desired Baud Rate Value on Value on all Bit 0 Power-on other resets Reset (Note1) RX9D 0000 -00x 0000 -00u TX9D 0000 --1x 0000 --1u xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
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... NA — HIGH 894.9 — LOW 3.496 — 1996 Microchip Technology Inc MHz OSC = 20 MHz SPBRG value %ERROR (decimal) KBAUD %ERROR — — NA — — — NA — — — NA — ...
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... NA — — 79.2 — 0 0.309 — OSC = 32.768 kHz SPBRG value KBAUD %ERROR (decimal) 0.256 -14. — — NA — — NA — — NA — — NA — — NA — — NA — — NA — — 0.512 — 0 0.002 — 255 1996 Microchip Technology Inc. ...
Page 89
... TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR is empty. Note: The TSR is not mapped in data memory not available to the user. 1996 Microchip Technology Inc. PIC17C4X Transmission is enabled by TXEN (TXSTA<5>) bit. The actual transmission will not ...
Page 90
... Transmit Shift Reg. Value on Value on all Bit 0 Power-on other resets Reset (Note1) RCIF 0000 0010 0000 0010 RX9D 0000 -00x 0000 -00u xxxx xxxx uuuu uuuu RCIE 0000 0000 0000 0000 TX9D 0000 --1x 0000 --1u xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
Page 91
... CLK x16 CLK 1996 Microchip Technology Inc. Note: The FERR and the 9th receive bit are buff- ered the same way as the receive data. Reading the RCREG register will allow the RX9D and FERR bits to be loaded with val- ues for the next received Received data; ...
Page 92
... RCREG Value on Value on all Bit 0 Power-on other resets Reset (Note1) RCIF 0000 0010 0000 0010 RX9D 0000 -00x 0000 -00u RX0 xxxx xxxx uuuu uuuu RCIE 0000 0000 0000 0000 TX9D 0000 --1x 0000 --1u xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
Page 93
... The RA4/RX/DT and RA5/TX/CK pins will revert to hi-impedance. If either CREN or SREN are set during a transmission, the transmission is aborted and the 1996 Microchip Technology Inc. PIC17C4X RA4/RX/DT pin reverts to a hi-impedance state (for a reception). The RA5/TX/CK pin will remain an output if the CSRC bit is set (internal clock) ...
Page 94
... Value on all Bit 0 Power-on other resets Reset (Note1) RCIF 0000 0010 0000 0010 RX9D 0000 -00x 0000 -00u TX0 xxxx xxxx uuuu uuuu RCIE 0000 0000 0000 0000 TX9D 0000 --1x 0000 --1u xxxx xxxx uuuu uuuu Word 2 bit6 bit7 1996 Microchip Technology Inc. ...
Page 95
... CREN bit RCIF bit Read RCREG Note: Timing diagram demonstrates SYNC master mode with SREN = 1. 1996 Microchip Technology Inc. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate. See Section 13.1 for details. ...
Page 96
... TRMT Value on Value on all Bit 0 Power-on other resets Reset (Note1) RCIF 0000 0010 0000 0010 RX9D 0000 -00x 0000 -00u RX0 xxxx xxxx uuuu uuuu RCIE 0000 0000 0000 0000 TX9D 0000 --1x 0000 --1u xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
Page 97
... Microchip Technology Inc. 13.4.2 USART SYNCHRONOUS SLAVE RECEPTION Operation of the synchronous master and slave modes are identical except in the case of the SLEEP mode. Also, SREN is a don't care in slave mode. ...
Page 98
... Value on Value on all Bit 0 Power-on other resets Reset (Note1) RCIF 0000 0010 0000 0010 RX9D 0000 -00x 0000 -00u RX0 xxxx xxxx uuuu uuuu RCIE 0000 0000 0000 0000 TX9D 0000 --1x 0000 --1u xxxx xxxx uuuu uuuu 1996 Microchip Technology Inc. ...
Page 99
... RC oscillator oscillator Note 1: This bit does not exist on the PIC17C42. Reading this bit will return an unknown value (x). 1996 Microchip Technology Inc. This document was created with FrameMaker The PIC17CXX has a Watchdog Timer which can be shut off only through EPROM bits. It runs off its own RC oscillator for added reliability ...
Page 100
... RESONATOR OPERATION ( OSC CONFIGURATION) C1 (1) XTAL Note1 C2 See Table 14-2 and Table 14-3 for recommended values of C1 and C2. Note 1: A series resistor may be required for AT strip cut crystals. oscillation (Figure 14-2). The OSC1 SLEEP RF OSC2 To internal logic PIC17CXX 1996 Microchip Technology Inc. ...
Page 101
... MHz Murata Erie CSA2.00MG 4.0 MHz Murata Erie CSA4.00MG 8.0 MHz Murata Erie CSA8.00MT 16.0 MHz Murata Erie CSA16.00MX Resonators used did not have built-in capacitors. 1996 Microchip Technology Inc. TABLE 14-3: Osc Freq Type LF 32 kHz 1 MHz SLEEP 2 MHz ...
Page 102
... The oscillator frequency, divided available on the OSC2/CLKOUT pin, and can be used for test pur- poses or to synchronize other logic (see Figure 3-2 for waveform). FIGURE 14-7: RC OSCILLATOR MODE V DD Rext Cext PIC17CXX V SS OSC1 Fosc/4 Internal OSC1 clock PIC17CXX OSC2/CLKOUT 1996 Microchip Technology Inc. ...
Page 103
... WDT) and pre- vent it from timing out thus generating a device RESET condition. The TO bit in the CPUSTA register will be cleared upon a WDT time-out. 1996 Microchip Technology Inc. PIC17C4X 14.3.2 CLEARING THE WDT AND POSTSCALER The WDT and postscaler are cleared when: • ...
Page 104
... DS30412C-page 104 Postscaler MUX WDT Overflow Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — PM0 WDTPS1 WDTPS0 FOSC1 STKAV GLINTD TO PD — WDTPS1:WDTPS0 Value on Value on all Bit 0 Power-on other resets Reset (Note1) FOSC0 (Note 2) (Note 2) — --11 11-- --11 qq-- 1996 Microchip Technology Inc. ...
Page 105
... When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 1996 Microchip Technology Inc. PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if WDT time-out occurred (and caused wake-up) ...
Page 106
... Note: Microchip does not recommend code pro- tecting windowed devices. If the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 1996 Microchip Technology Inc. microcontroller ...
Page 107
... Thus, for an oscillator frequency of 25 MHz, the normal instruction execution time is 160 ns conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 320 ns. 1996 Microchip Technology Inc. This document was created with FrameMaker PIC17C4X TABLE 15-1: ...
Page 108
... The user 0 should keep this in mind when operating on special function registers, such as ports ALUSTA will clear register PCH PCLATH; PCL dest PCLATH PCH; 8-bit destination value PCL PCL ALU operand PCLATH PCH; 8-bit result PCL 1996 Microchip Technology Inc. ...
Page 109
... Q cycles to the instruction cycle. FIGURE 15-2: Q CYCLE ACTIVITY Q1 Q2 Tosc Tcy1 1996 Microchip Technology Inc. The 4 Q cycles that make up an instruction cycle (Tcy) can be generalized as: Q1: Instruction Decode Cycle or forced NOP Q2: Instruction Read Cycle or NOP Q3: Instruction Execute ...
Page 110
... OV,C,DC,Z 0000 010d ffff ffff 1 OV,C,DC,Z 0000 001d ffff ffff 1 0001 110d ffff ffff 2 (3) 1010 10ti ffff ffff 1996 Microchip Technology Inc. Notes Z None 3 Z None 6,8 None 2,6,8 None 2,6 None ...
Page 111
... Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles “skip” means that instruction fetched during execution of current instruction is not executed, instead an NOP is executed. 9: These instructions are not available on the PIC17C42. 1996 Microchip Technology Inc. PIC17C4X Cycles 16-bit Opcode ...
Page 112
... ADD WREG label ] ADDWF f 255 d (WREG) + (f) (dest) OV, C, DC, Z 0000 111d ffff ffff Add WREG to register 'f the result is stored in WREG the result is stored back in register 'f Read Execute Write to register 'f' destination ADDWF REG 0x17 = 0xC2 = 0xD9 = 0xC2 1996 Microchip Technology Inc. ...
Page 113
... REG 0 Before Instruction Carry bit = 1 REG = 0x02 WREG = 0x4D After Instruction Carry bit = 0 REG = 0x02 WREG = 0x50 1996 Microchip Technology Inc. ANDLW f,d Syntax: Operands: Operation: (dest) Status Affected: Encoding: ffff ffff Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q4 Write to Example: destination ...
Page 114
... Q Cycle Activity: Q1 Decode Q4 Example: Write to destination Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 Bit Clear f [ label ] BCF f 255 (f<b>) None 1000 1bbb ffff ffff Bit 'b' in register 'f' is cleared Read Execute Write register 'f' register 'f' BCF FLAG_REG, 7 1996 Microchip Technology Inc. ...
Page 115
... Words: 1 Cycles Cycle Activity Decode Read Execute register 'f' Example: BSF FLAG_REG, 7 Before Instruction FLAG_REG= 0x0A After Instruction FLAG_REG= 0x8A 1996 Microchip Technology Inc. BTFSC Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff Description: Q4 Write Words: register 'f' Cycles: Q Cycle Activity: Q1 Decode If skip: ...
Page 116
... After Instruction: PORTC = Q4 NOP Bit Toggle f [ label ] BTG f 255 0 b < 7 (f<b>) (f<b>) None 0011 1bbb ffff ffff Bit 'b' in data memory location 'f' is inverted Read Execute Write register 'f' register 'f' BTG PORTC, 4 0111 0101 [0x75] 0110 0101 [0x65] 1996 Microchip Technology Inc. ...
Page 117
... Read literal Execute 'k'<7:0> Forced NOP NOP Execute Example: HERE CALL THERE Before Instruction PC = Address(HERE) After Instruction PC = Address(THERE) TOS = Address (HERE + 1) 1996 Microchip Technology Inc. CLRF Syntax: Operands: PC<12:0>, Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q4 NOP ...
Page 118
... REG1 WREG Complement f [ label ] COMF f 255 d [0, (dest) Z 0001 001d ffff ffff The contents of register 'f' are comple- mented the result is stored in WREG the result is stored back in register 'f Read Execute Write register 'f' register 'f' COMF REG1,0 = 0x13 = 0x13 = 0xEC 1996 Microchip Technology Inc. ...
Page 119
... Before Instruction PC Address = HERE WREG = ? REG = ? After Instruction If REG = WREG Address (EQUAL) If REG WREG Address (NEQUAL) 1996 Microchip Technology Inc. CPFSGT f Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff Description: Words: Cycles: Q Cycle Activity NOP Decode If skip NOP Forced NOP Example: ...
Page 120
... BCD format) and produces a correct packed BCD result Result is placed in Data memory location 'f' and WREG Result is placed in Data memory location 'f Read Execute Write register 'f' register 'f' and other specified register DAW REG1 0xA5 = ?? = 0x05 = 0x05 = 0xCE = ?? = 0x24 = 0x24 = 1996 Microchip Technology Inc. ...
Page 121
... Decode Read Execute register 'f' Example: DECF CNT, 1 Before Instruction CNT = 0x01 After Instruction CNT = 0x00 1996 Microchip Technology Inc. DECFSZ Syntax: Operands: Operation: Status Affected: ffff ffff Encoding: Description: Q4 Write to Words: destination Cycles: Q Cycle Activity: Q1 Decode Example: Before Instruction PC After Instruction ...
Page 122
... The thirteen bit immediate value is loaded into PC bits <12:0>. Then the upper eight bits of PC are loaded into PCLATH. GOTO is always a two-cycle instruction Read literal Execute NOP 'k'<7:0> NOP Execute NOP GOTO THERE Address (THERE) 1996 Microchip Technology Inc. ...
Page 123
... Example: INCF CNT, 1 Before Instruction CNT = 0xFF After Instruction CNT = 0x00 1996 Microchip Technology Inc. INCFSZ Syntax: Operands: Operation: Status Affected: ffff ffff Encoding: Description: Q4 Words: Write to destination Cycles: Q Cycle Activity: Q1 Decode If skip: Q1 Forced NOP Example: Before Instruction PC After Instruction ...
Page 124
... Inclusive OR Literal with WREG [ label ] IORLW 255 (WREG) .OR. (k) (WREG) Z 1011 0011 kkkk kkkk The contents of WREG are OR’ed with the eight bit literal 'k'. The result is placed in WREG Read Execute Write to literal 'k' WREG IORLW 0x35 = 0x9A = 0xBF 1996 Microchip Technology Inc. ...
Page 125
... Decode Read Execute register 'f' Example: IORWF RESULT, 0 Before Instruction RESULT = 0x13 WREG = 0x91 After Instruction RESULT = 0x13 WREG = 0x93 1996 Microchip Technology Inc. LCALL f,d Syntax: Operands: Operation: (dest) Status Affected: Encoding: ffff ffff Description: Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 ...
Page 126
... Bank Select Register (BSR). Only the low 4-bits of the Bank Select Register are affected. The upper half of the BSR is unchanged. The assembler will encode the “u” fields as '0 Read Execute Write literal literal 'u:k' 'k' to BSR<3:0> MOVLB 0x5 = 0x22 = 0x25 1996 Microchip Technology Inc. ...
Page 127
... Example: MOVLR 5 Before Instruction BSR register = 0x22 After Instruction BSR register = 0x52 Note: This instruction is not available in the PIC17C42 device. 1996 Microchip Technology Inc. MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk uuuu Description: Words: Cycles: Q Cycle Activity: Q1 Decode Example: ...
Page 128
... Write register 'f' Move WREG label ] MOVWF 255 (WREG) (f) None 0000 0001 ffff ffff Move data from WREG to register 'f'. Location 'f' can be anywhere in the 256 word data space Read Execute Write register 'f' register 'f' MOVWF REG = 0x4F = 0xFF = 0x4F = 0x4F 1996 Microchip Technology Inc. ...
Page 129
... PRODH = ? PRODL = ? After Instruction WREG = 0xC4 PRODH = 0xAD PRODL = 0x08 Note: This instruction is not available in the PIC17C42 device. 1996 Microchip Technology Inc. MULWF k Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Q Cycle Activity Write Decode registers PRODH: ...
Page 130
... Syntax: Operands: Operation: Status Affected: Encoding: Description: ffff ffff Words: Cycles: Q Cycle Activity: Q1 Decode Example: None. Q4 Write register 'f' and other specified register No Operation [ label ] NOP None No operation None 0000 0000 0000 0000 No operation NOP Execute NOP 1996 Microchip Technology Inc. ...
Page 131
... Q Cycle Activity Decode Read Execute register T0STA Forced NOP NOP Execute Example: RETFIE After Interrupt PC = TOS GLINTD = 0 1996 Microchip Technology Inc. RETLW Syntax: Operands: Operation: Status Affected: Encoding: 0000 0101 Description: Words: Cycles: Q Cycle Activity Decode NOP Forced NOP Example: NOP ...
Page 132
... The contents of register 'f' are rotated one bit to the left through the Carry Flag the result is placed in WREG the result is stored back in register 'f'. C register Read Execute Write to register 'f' destination RLCF REG,0 = 1110 0110 = 0 = 1110 0110 = 1100 1100 = 1 1996 Microchip Technology Inc. ...
Page 133
... Decode Read Execute register 'f' Example: RLNCF REG, 1 Before Instruction REG = 1110 1011 After Instruction C = REG = 1101 0111 1996 Microchip Technology Inc. RRCF f,d Syntax: Operands: Operation: Status Affected: ffff ffff Encoding: Description: Words: Cycles Cycle Activity: Write to Q1 destination Decode Example: ...
Page 134
... If ' both the data memory location 'f' and WREG are set to FFh only the data memory location 'f' is set to FFh Read Execute Write register 'f' register 'f' and other specified register SETF REG 0xDA = 0x05 = 0xFF = 0xFF SETF REG 0xDA = 0x05 = 0xFF = 0x05 1996 Microchip Technology Inc. ...
Page 135
... Read Execute register PCLATH Example: SLEEP Before Instruction After Instruction † † If WDT causes wake-up, this bit is cleared 1996 Microchip Technology Inc. SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: 0000 0011 Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction WREG ...
Page 136
... SUBWFB REG1,0 = 0x1B (0001 1011) = 0x1A (0001 1010 0x1B (0001 1011) = 0x00 = 1 ; result is zero = 1 SUBWFB REG1,1 = 0x03 (0000 0011) = 0x0E (0000 1101 0xF5 (1111 0100) [2’s comp] = 0x0E (0000 1101 result is negative = 0 1996 Microchip Technology Inc. ...
Page 137
... Q Cycle Activity Decode Read Execute register 'f' Example: SWAPF REG, 0 Before Instruction REG = 0x53 After Instruction REG = 0x35 1996 Microchip Technology Inc. TABLRD Syntax: Operands: Operation: ffff ffff Status Affected: Encoding: Description: Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode PIC17C4X Table Read ...
Page 138
... The TBLPTR can be automati- cally incremented TBLPTR is not incremented TBLPTR is incremented Words: 1 Cycles: 2 (many if write is to on-chip EPROM program memory) Q Cycle Activity Decode Read Execute register 'f' 1996 Microchip Technology Inc. ffff ffff then the Q4 Write register TBLATH or TBLATL ...
Page 139
... TBLPTR = 0xA356 MEMORY(TBLPTR) = 0xAA53 Program 15 0 Memory TBLPTR bits TBLAT 1996 Microchip Technology Inc. TLRD Table Latch Read Syntax: [ label ] TLRD t,f Operands Operation Status Affected: None Encoding: Description: Read data from 16-bit table latch (TBLAT) into file register 'f'. Table Latch is unaffected ...
Page 140
... If ' the next instruction, fetched during the current instruction execution, is discarded and an NOP is executed making this a two-cycle instruction ( Read Execute NOP register ' NOP Execute NOP HERE TSTFSZ CNT NZERO : ZERO : = 0x00, = Address (ZERO) 0x00, = Address (NZERO) 1996 Microchip Technology Inc. ...
Page 141
... Q Cycle Activity Decode Read Execute literal 'k' Example: XORLW 0xAF Before Instruction WREG = 0xB5 After Instruction WREG = 0x1A 1996 Microchip Technology Inc. XORWF Syntax: Operands: Operation: WREG) Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Q Cycle Activity Write to Decode WREG Example: ...
Page 142
... PIC17C4X NOTES: DS30412C-page 142 1996 Microchip Technology Inc. ...
Page 143
... Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user compliant version of PICMASTER is available for European Union (EU) countries. 1996 Microchip Technology Inc. This document was created with FrameMaker ICEPIC: Low-cost PIC16CXXX 16.3 In-Circuit Emulator ...
Page 144
... PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. 1996 Microchip Technology Inc. ...
Page 145
... MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy TECH-MP, edition for imple- menting more complex systems. 1996 Microchip Technology Inc. Both versions include Microchip’s fuzzy LAB System stration board for hands-on experience with fuzzy logic systems implementation ...
Page 146
... PIC17C4X TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP DS30412C-page 146 1996 Microchip Technology Inc. ...
Page 147
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1996 Microchip Technology Inc. This document was created with FrameMaker Applicable Devices 42 R42 42A 43 R43 44 ...
Page 148
... Freq: 4 MHz max 4. max max. at 5.5V (WDT disabled) PD Freq: 25 MHz max 4. max max. at 5.5V (WDT disabled) PD Freq: 25 MHz max 4. 150 A max kHz (WDT enabled max. at 5.5V (WDT disabled) PD Freq: 2 MHz max. 1996 Microchip Technology Inc. ...
Page 149
... For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 PIC17C42-16 (Commercial, Industrial) PIC17C42-25 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 150
... A T +70˚C for commercial A Conditions Note1 Note1 A Vss PIN DD I/O Pin at hi-impedance PORTB weak pull-ups dis- abled Vss PIN PIN DD A Vss 12V Vss V V PIN 12V MCLR PP (when not programming RBPU = 0 PIN SS 1996 Microchip Technology Inc. ...
Page 151
... The MCLR/Vpp pin may be kept in this range at times other than programming, but this is not recommended. 6: For TTL buffers, the better of the two specifications may be used. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 152
... Operating voltage V range as described in Section 17.1 DD Min Typ† Max pin 12.75 – 13.25 PP 4.75 5.0 5.25 pin – 25 ‡ 50 ‡ PP – – 30 ‡ 10 100 1000 T +40˚C A Units Conditions V Note Terminated via internal/exter- nal interrupt or a reset 1996 Microchip Technology Inc. ...
Page 153
... I/O port mc MCLR OSC1 Uppercase symbols and their meanings Driven E Edge F Fall H High I Invalid (Hi-impedance) 1996 Microchip Technology Inc. PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 T Time ost Oscillator Start-up Timer pwrt Power-up Timer rb PORTB T0CKI t123 TCLK12 and TCLK3 wdt ...
Page 154
... LOAD CONDITIONS Load Condition Pin V SS DS30412C-page 154 Data in valid Data in invalid Data in valid Data in invalid 0.25V 0.25V 0.25V 0.25V Output driven Output Data out invalid hi-impedance 0.9V DD Rise Time Fall Time Load Condition Pin 464 1996 Microchip Technology Inc. ...
Page 155
... All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 ...
Page 156
... T . OSC new value Max Units Conditions 30 ‡ ns Note 1 30 ‡ ns Note 1 15 ‡ ns Note 1 15 ‡ ns Note 1 0.5T + 20‡ ns Note 1 CY — ns Note 1 — ns Note 1 100 ‡ ‡ ‡ ns — ns — ns 1996 Microchip Technology Inc. ...
Page 157
... Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ These parameters are for design guidance only and are not tested, nor characterized. § This specification ensured by design. 1996 Microchip Technology Inc. PIC17C4X Applicable Devices 42 R42 42A 43 R43 Min Typ† ...
Page 158
... With Prescaler 10* — § — Typ Min † 0 § — § — § — § — OSC — ns — ns — ns — ns — prescale value ( ..., 256) 48 Max Units Conditions — ns — ns — prescale value ( Tosc § — 1996 Microchip Technology Inc. ...
Page 159
... These parameters are characterized but not tested. † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 Min Typ† ...
Page 160
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. DS30412C-page 160 121 Min — — — 125 126 Min 15 15 122 Typ† Max Units Conditions — Typ† Max Units Conditions — — ns — — ns 1996 Microchip Technology Inc. ...
Page 161
... These parameters are characterized but not tested. † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification is guaranteed by design. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 151 ...
Page 162
... Q1 Q2 161 Addr out 163 '1' Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns § — — — § — — 0. — 0 1996 Microchip Technology Inc. ...
Page 163
... C) OSC 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0. 1996 Microchip Technology Inc. This document was created with FrameMaker Applicable Devices 42 R42 42A 43 R43 44 Typical Capacitance (pF) 44-pin PLCC 44-pin MQFP Frequency normalized to +25 C Rext 10 k Cext = 100 3.5V ...
Page 164
... FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Cext = 100 pF 0.5 0.0 4.0 4.5 DS30412C-page 164 DD Cext = 22 pF 100k 5.0 5.5 V (Volts 3. 5. 10k R = 100k 5.0 5.5 V (Volts) DD 6.0 6.5 6.0 6.5 1996 Microchip Technology Inc. ...
Page 165
... Cext = 300 pF 0.2 0.0 4.0 4.5 TABLE 18-2: RC OSCILLATOR FREQUENCIES Cext 22 pF 100 pF 300 pF 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 3. 5. 10k R = 160k 5.0 5.5 V (Volts) DD Rext Fosc @ 5V 10k 3.33 MHz 100k 353 kHz 3 ...
Page 166
... FIGURE 18-6: TRANSCONDUCTANCE (gm OSCILLATOR vs 2.5 3.0 DS30412C-page 166 Max @ -40 C Typ @ 25 C 3.5 4.0 4.5 5.0 V (Volts) DD Max @ -40 C 3.5 4.0 4.5 5.0 V (Volts Min @ 85 C 5.5 6.0 DD Typ @ 25 C Min @ 85 C 5.5 6.0 1996 Microchip Technology Inc. ...
Page 167
... FREQUENCY (EXTERNAL CLOCK 125 100000 10000 7.0V 1000 6.5V 6.0V 5.5V 5.0V 4.5V 4.0V 100 10k 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 100k 1M External Clock Frequency (Hz) 100k 1M External Clock Frequency (Hz) PIC17C4X 10M 100M 10M 100M DS30412C-page 167 ...
Page 168
... Temp 1100 1000 900 800 700 600 500 Temp 400 300 200 100 0 4.0 4.5 DS30412C-page 168 WATCHDOG DISABLED 5.0 5.5 6.0 V (Volts) DD WATCHDOG DISABLED DD Temp 5.0 5.5 6.0 V (Volts) DD 6.5 7.0 Temp. = -40 C 6.5 7.0 1996 Microchip Technology Inc. ...
Page 169
... FIGURE 18-11: TYPICAL I vs 4.0 4.5 FIGURE 18-12: MAXIMUM I vs 4.0 4.5 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 WATCHDOG ENABLED 5.0 5.5 6.0 V (Volts) DD WATCHDOG ENABLED DD 5.0 5.5 6.0 V (Volts) DD PIC17C4X 6.5 7.0 - 6.5 7.0 DS30412C-page 169 ...
Page 170
... FIGURE 18-13: WDT TIMER TIME-OUT PERIOD vs Max Max Min Min. - 4.0 4.5 FIGURE 18-14 Min @ Typ @ 25 C -10 -12 -14 Max @ -40 C -16 -18 0.0 0.5 DS30412C-page 170 DD Typ 5.0 5.5 6.0 V (Volts) DD 1.0 1.5 2.0 V (Volts) DD 6.5 7.0 2.5 3.0 1996 Microchip Technology Inc. ...
Page 171
... Typ @ 25 C -30 -35 0.0 0.5 1.0 FIGURE 18-16 0.0 0.5 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 Min @ 85 C 1.5 2.0 2.5 3.0 3.5 V (Volts) DD Max. -40 C Typ Min. +85 C 1.0 1.5 2.0 V (Volts) DD PIC17C4X Max @ -40 C 4.0 4 ...
Page 172
... THRESHOLD VOLTAGE) OF I/O PINS (TTL) TH 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 2.5 3.0 DS30412C-page 172 Max @ -40 C 1.0 1.5 2.0 V (Volts) DD Max (- +85 C) Typ @ 25 C Min (- +85 C) 3.5 4.0 4.5 5.0 V (Volts) DD Typ @ 25 C Min @ +85 C 2.5 3 5.5 6.0 1996 Microchip Technology Inc. ...
Page 173
... FIGURE 18-20: V (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT TH (IN XT AND LF MODES) vs. V 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 max (- + typ ( min (- + 3.0 3.5 4.0 4.5 V ...
Page 174
... PIC17C4X NOTES: DS30412C-page 174 1996 Microchip Technology Inc. ...
Page 175
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1996 Microchip Technology Inc. This document was created with FrameMaker Applicable Devices 42 R42 42A 43 R43 44 ...
Page 176
... PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 TABLE 19-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) DS30412C-page 176 1996 Microchip Technology Inc. ...
Page 177
... SLEEP mode, with all I/O pins in hi-impedance state and tied For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial) PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial) PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial) ...
Page 178
... A T +70˚C for commercial A Conditions Device in SLEEP mode See section on Power-on Reset for details details MHz (Note 4) OSC MHz OSC kHz, OSC WDT disabled (EC osc configuration 5.5V, WDT enabled 5.5V, WDT disabled T0CKI = V , MCLR R 1996 Microchip Technology Inc. ...
Page 179
... The MCLR/V pin may be kept in this range at times other than programming, but is not recommended For TTL buffers, the better of the two specifications may be used. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial) PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial) PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial) ...
Page 180
... osc modes when OSC2 pin is outputting CLKOUT. external clock is used to drive OSC1. – – – – Microprocessor or Extended Microcontroller mode 1996 Microchip Technology Inc. +85˚C for industrial and +70˚C for commercial Conditions = V /1.250 6. 60.0 mA 6.0V OL ...
Page 181
... For TTL buffers, the better of the two specifications may be used. Note: When using the Table Write for internal programming, the device temperature must be less than 40˚C. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 182
... S D Driven E Edge F Fall H High I Invalid (Hi-impedance) DS30412C-page 182 specifications only specifications only) T Time ost Oscillator Start-Up Timer pwrt Power-Up Timer rb PORTB T0CKI t123 TCLK12 and TCLK3 wdt Watchdog Timer Low P Period R Rise V Valid Z Hi-impedance 1996 Microchip Technology Inc. ...
Page 183
... All other input pins OUTPUT LEVEL CONDITIONS Data out valid 0 LOAD CONDITIONS 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 Data in valid Data in invalid Data in valid Data in invalid 0.25V 0.25V 0.25V 0.25V Output driven Output Data out invalid hi-impedance 0 ...
Page 184
... MHz devices devices (25 MHz devices devices (33 MHz devices devices (16 MHz devices devices (25 MHz devices devices (33 MHz devices devices (16 MHz devices devices (25 MHz devices devices (33 MHz devices devices (16 MHz devices devices (25 MHz devices devices (33 MHz devices) 1996 Microchip Technology Inc. ...
Page 185
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ These parameters are for design guidance only and are not tested, nor characterized. Note 1: Measurements are taken in EC Mode where CLKOUT output 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 ...
Page 186
... This specification ensured by design. DS30412C-page 186 30 35 Min Typ† Max 100 * — — 1024T § OSC 200 * PIC17CR42/42A/ — — 100 * 43/R43/44 PIC17LCR42/ — — 120 * 42A/43/R43/44 31 Units Conditions — — OSC1 period OSC 1996 Microchip Technology Inc. ...
Page 187
... These parameters are characterized but not tested. † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 Min No Prescaler 0 ...
Page 188
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. DS30412C-page 188 Min Typ† Max Units Conditions 10 * — — 2T § — Min Typ† Max Units Conditions — *§ — *§ — ns — ns — prescale value ( 1996 Microchip Technology Inc. ...
Page 189
... TckL2dtl Data hold after CK (DT hold time) † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 121 122 PIC17CR42/42A/43/R43/44 PIC17LCR42/42A/43/R43/44 ...
Page 190
... DS30412C-page 190 151 150 154 addr out data out 152 Min 0.25Tcy - 10 0 0.25Tcy - 40 — 0.25T — 0.25T Q2 Q1 addr out 153 Typ† Max Units Conditions — — ns — — ns — — ns § — § — 1996 Microchip Technology Inc. ...
Page 191
... These parameters are characterized but not tested. † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 166 ...
Page 192
... PIC17C4X NOTES: DS30412C-page 192 1996 Microchip Technology Inc. ...
Page 193
... C) OSC 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0. 1996 Microchip Technology Inc. This document was created with FrameMaker Applicable Devices 42 R42 42A 43 R43 44 Typical Capacitance (pF) 44-pin PLCC 44-pin MQFP Frequency normalized to +25 C Rext 10 k Cext = 100 3.5V ...
Page 194
... FIGURE 20-3: TYPICAL RC OSCILLATOR FREQUENCY vs. V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Cext = 100 pF 0.5 0.0 4.0 4.5 DS30412C-page 194 DD Cext = 22 pF 100k 5.0 5.5 V (Volts 3. 5. 10k R = 100k 5.0 5.5 V (Volts) DD 6.0 6.5 6.0 6.5 1996 Microchip Technology Inc. ...
Page 195
... Cext = 300 pF 0.2 0.0 4.0 4.5 TABLE 20-2: RC OSCILLATOR FREQUENCIES Cext 22 pF 100 pF 300 pF 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 3. 5. 10k R = 160k 5.0 5.5 V (Volts) DD Rext Fosc @ 5V 10k 3.33 MHz 100k 353 kHz 3 ...
Page 196
... FIGURE 20-6: TRANSCONDUCTANCE (gm OSCILLATOR vs 2.5 3.0 DS30412C-page 196 Max @ -40 C Typ @ 25 C 3.5 4.0 4.5 5.0 V (Volts) DD Max @ -40 C 3.5 4.0 4.5 5.0 V (Volts Min @ 85 C 5.5 6.0 DD Typ @ 25 C Min @ 85 C 5.5 6.0 1996 Microchip Technology Inc. ...
Page 197
... FREQUENCY (EXTERNAL CLOCK 125 100000 10000 1000 7.0V 6.5V 6.0V 5.5V 5.0V 4.5V 4.0V 100 10k 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 100k 1M External Clock Frequency (Hz) 100k 1M External Clock Frequency (Hz) PIC17C4X 10M 100M 10M 100M DS30412C-page 197 ...
Page 198
... Temp 1000 900 800 700 600 500 Temp 400 300 200 100 0 4.0 4.5 DS30412C-page 198 WATCHDOG DISABLED 5.0 5.5 6.0 V (Volts) DD WATCHDOG DISABLED DD Temp 5.0 5.5 6.0 V (Volts) DD 6.5 7.0 Temp. = -40 C 6.5 7.0 1996 Microchip Technology Inc. ...
Page 199
... FIGURE 20-11: TYPICAL I vs 4.0 4.5 FIGURE 20-12: MAXIMUM I vs 4.0 4.5 1996 Microchip Technology Inc. Applicable Devices 42 R42 42A 43 R43 44 WATCHDOG ENABLED 5.0 5.5 6.0 V (Volts) DD WATCHDOG ENABLED DD 5.0 5.5 6.0 V (Volts) DD PIC17C4X 6.5 7.0 - 6.5 7.0 DS30412C-page 199 ...
Page 200
... FIGURE 20-13: WDT TIMER TIME-OUT PERIOD vs Max Max Min Min. - 4.0 4.5 FIGURE 20-14 Min @ Typ @ 25 C -10 -12 -14 Max @ -40 C -16 -18 0.0 0.5 DS30412C-page 200 DD Typ 5.0 5.5 6.0 V (Volts) DD 1.0 1.5 2.0 V (Volts) DD 6.5 7.0 2.5 3.0 1996 Microchip Technology Inc. ...