PIC17C42A-33I/PQ Microchip Technology, PIC17C42A-33I/PQ Datasheet - Page 84

• Manufacturer Part Number: PIC17C42A-33I/PQ
• Description: IC MCU OTP 2KX16 PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C42A-33I/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: OTP
• Ram Size: 232 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 232 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• For Use With: AC164316 - MODULE SKT MPLAB PM3 44MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC17C4X
FIGURE 13-2: RCSTA REGISTER (ADDRESS: 13h, BANK 0)
DS30412C-page 84
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN
SPEN : Serial Port Enable bit
1 = Configures RA5/RX/DT and RA4/TX/CK pins as serial port pins
0 = Serial port disabled
RX9 : 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN : Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
CREN : Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable reception
0 = Disables reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
Unimplemented : Read as '0'
FERR : Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
OERR : Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D : 9th bit of receive data (can be the software calculated parity bit)
RX9
SREN
CREN
U - 0
—
FERR
R - 0
OERR
R - 0
RX9D
R - x
bit 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
1996 Microchip Technology Inc.