ATTINY2313-20SI Atmel, ATTINY2313-20SI Datasheet - Page 109

• Manufacturer Part Number: ATTINY2313-20SI
• Description: IC MCU AVR 2K FLASH 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313-20SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATTINY2313-24SI; ATTINY2313-24SI

Output Compare
Register 1 B -
OCR1BH and OCR1BL
Input Capture Register
1 – ICR1H and ICR1L
Timer/Counter
Interrupt Mask
Register – TIMSK
2543L–AVR–08/10
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 84.
See “Accessing 16-bit Registers” on page 84.
TOIE1
R/W
R/W
R/W
7
0
7
0
7
0
(See “Interrupts” on page
(See “Interrupts” on page
OCIE1A
R/W
R/W
R/W
6
0
6
0
6
0
44.) is executed when the TOV1 flag, located in TIFR, is set.
OCIE1B
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
OCR1B[15:8]
4
0
4
0
OCR1B[7:0]
R
4
–
0
ICR1[15:8]
ICR1[7:0]
44.) is executed when the OCF1A flag, located in
44.) is executed when the OCF1B flag, located in
R/W
R/W
ICIE1
R/W
3
0
3
0
3
0
OCIE0B
R/W
R/W
R/W
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
1
0
1
0
1
0
OCIE0A
R/W
R/W
R/W
0
0
0
0
0
0
OCR1BH
OCR1BL
ICR1H
ICR1L
TIMSK
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