ATTINY2313-20SI Atmel, ATTINY2313-20SI Datasheet - Page 30

• Manufacturer Part Number: ATTINY2313-20SI
• Description: IC MCU AVR 2K FLASH 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313-20SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATTINY2313-24SI; ATTINY2313-24SI

Power
Management
and Sleep
Modes
MCU Control Register
– MCUCR
Idle Mode
30
ATtiny2313
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register select
which sleep mode (Idle, Power-down, or Standby) will be activated by the SLEEP instruction.
See
the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, exe-
cutes the interrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Figure 11 on page 22
tion. The figure is helpful in selecting an appropriate sleep mode.
The Sleep Mode Control Register contains control bits for power management.
• Bits 6, 4 – SM1..0: Sleep Mode Select Bits 1 and 0
These bits select between the five available sleep modes as shown in
Table 13. Sleep Mode Select
Note:
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the UART, Analog Comparator, ADC, USI, Timer/Counters,
Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and UART Transmit Complete interrupts. If wake-up from the Ana-
log Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode.
Bit
Read/Write
Initial Value
CPU
Table 13
SM1
0
0
1
1
and clk
1. Standby mode is only recommended for use with external crystals or resonators.
FLASH
for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode,
PUD
R/W
7
0
SM0
, while allowing the other clocks to run.
0
1
0
1
presents the different clock systems in the ATtiny2313, and their distribu-
SM1
R/W
6
0
Sleep Mode
Idle
Power-down
Standby
Power-down
R/W
SE
5
0
SM0
R/W
0
4
ISC11
R/W
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
Table
ISC00
R/W
0
0
13.
MCUCR
2543L–AVR–08/10