AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 5

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. Pin Description
Table 4-1.
6048C–ATARM–29-Jun-06
Module
EBI
GIC
Power-on
Reset
Master
Clock
Real-time
Clock
UPIO
USART0
USART1
USART2
Capture
PWM
(2)
Name
ADD[19:1]
ADD0/NLB
ADD20/CS7
ADD21/CS6
D[15:0]
NOE/NRD
NWR0/NWE
NCS[3:0]
NWR1/NUB
NWAIT
IRQ0
FIQ
NRESET
MCKI
MCKO
PLLRC
RTCKI
RTCKO
UPIO[17:0]
SCK0/MPIO
RXD0/MPIO
TXD0/MPIO
SCK1/MPIO
RXD1/MPIO
TXD1/MPIO
SCK2/MPIO
RXD2/MPIO
TXD2/MPIO
CAPT[1:0]/MPIO
PWM[3:0]/MPIO
Pin Description
(3)
Function
External address bus
External address line/Lower
byte enable
External address line/Chip
select
External address line/Chip
select
External data bus
Output enable
Write enable
Chip select lines
Upper byte enable
Wait Input
External interrupt line
Fast interrupt line
Hardware reset input
Master clock input
Master clock output
PLL RC network input
32.768 kHz clock input
32.768 kHz clock output
Unified I/O
USART0 clock line
USART0 receive line
USART0 transmit line
USART1 clock line
USART1 receive line
USART1 transmit line
USART2 clock line
USART2 receive line
USART2 transmit line
Capture input
Pulse Width Modulation output
Type
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O (I)
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
(1)
Level
H (Z)
H (Z)
L (Z)
L (Z)
L (Z)
L (Z)
L (Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
L
L
(1)
Comments
The EBI is tri-stated when NRESET is
at a logical low level. Internal pull-
downs on data bus bits. ADD20 and
ADD21 are address lines at reset.
Internal pull-up (must be connected to
VCC or leave unconnected for normal
operation)
Schmitt input with internal filter
Connected to external crystal (4 to 16
MHz)
Connected to external 32.768 kHz
crystal
General-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
Multiplexed with general-purpose I/O
AT91SAM7A1
5