AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 8

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. Generic Interrupt Controller (GIC)
9. Parallel I/O Controller (PIO)
10. Peripheral Data Controller (PDC)
11. Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
8
AT91SAM7A1
The AT91SAM7A1 has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real time overhead in handling internal and
external interrupts. The interrupt controller is connected to the nFIQ (fast interrupt request) and
the nIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor's nFIQ
line can only be asserted by the external fast interrupt request input, the FIQ. The nIRQ line can
be asserted by the interrupts generated by the on-chip peripherals and the external interrupt
request line, IRQ0. An 8-level priority encoder allows the customer to define the priority between
the different nIRQ interrupt sources. Internal sources are programmed to be level sensitive or
edge triggered. External sources can be programmed to be positive or negative edge triggered
or high or low level sensitive.
The AT91SAM7A1 has 49 configurable I/O lines. Thirty-two pins (unified PIO) on the
AT91SAM7A1 are dedicated as general purpose I/O pins (UPIO0 - UPIO31). Other I/O lines are
multiplexed with an external signal of a peripheral to optimize the use of available package pins.
The unified PIO pins are controlled by a dedicated module; the others pins are configured in
each module.
An on-chip, 11-channel Peripheral Data Controller (PDC) transfers data between the on-chip
peripherals and the on- and off-chip memories without processor intervention. One PDC channel
is connected to the receiving channel and one to the transmitting channel of each USART and of
the SPI. A single PDC channel is connected to each ADC and each Capture.
Most importantly, the PDC removes the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data transfer. It can transfer up to 64 Kbytes
without reprogramming the starting address. As a result, the performance of the microcontroller
is increased and the power consumption reduced.
The AT91SAM7A1 provides three identical, full-duplex Universal Synchronous/Asynchronous
Receiver/Transmitters that are connected to the Peripheral Data Controller. The main features
are:
• Programmable Baud Rate Generator
• Parity, framing and overrun error detection
• Line break generation and detection
• Automatic echo, local & remote loopback modes
• Multi-drop mode: address detection and generation
• Interrupt generation
• Two Dedicated Peripheral Data Controller channels
• 5-, 6-, 7-, 8- and 9-bit character length
• Idle flag for J1587 protocol.
• Smart card transmission error feature
• Support LIN 1.2 protocol with H/W layer
6048C–ATARM–29-Jun-06