AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet
AT91SAM7A1-AU
Specifications of AT91SAM7A1-AU
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AT91SAM7A1-AU Summary of contents
Page 1
... CPU and Peripherals Can Be Deactivated Individually • Fully Static Operation MHz – 3.0V to 3.6V Core, Memory and Analog Voltage Range – 3 5.5V Compliant I/Os – -40° to +85°C Operating Temperature Range • Available in a 144-pin LQFP AT91 ARM Thumb-based Microcontroller AT91SAM7A1 6048B–ATARM–29-Jun-06 ...
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... The device is manufactured using high-density CMOS technology. By combining the ARM7TDMI processor with an on-chip RAM and a wide range of peripheral functions on a monolithic chip, the AT91SAM7A1 is a powerful device that provides a flexible, cost-effective solution to many compute-intensive embedded control applications in the indus- trial world. ...
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... LQFP Package Pinout Table 2-1. AT91SAM7A1 Pinout for 144-lead LQFP Package Pin Name VDD3V (I/O) 6 GND3V (I/O+CORE) 7 VDD3V (I/O+CORE D10 D11 D12 D13 D14 D15 20 ADD17 21 ADD16 22 NWR0/NWE 23 ADD19 24 ADD18 25 ADD7 26 ADD6 27 GND3V (I/O+CORE) 28 VDD3V (I/O+CORE) 29 ADD2 30 ADD3 31 ADD4 ...
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... RTCKO 32.768 kHz clock output UPIO[17:0] Unified I/O SCK0/MPIO USART0 clock line RXD0/MPIO USART0 receive line TXD0/MPIO USART0 transmit line AT91SAM7A1 4 (1) (1) Type Level Comments (2) EBI The EBI is tri-stated when NRESET logical low level. Internal pull-downs on data bus ...
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... I/O (I) (Z) Multiplexed with a general purpose I/O CAN0 (H) JTAG Internal pull-down (must be connected to GND leave unconnected for normal operation) I Schmitt trigger, internal pull- Schmitt trigger, internal pull-up I Schmitt trigger, internal pull-up Internal pull-down (must be connected to GND leave unconnected for normal operation) AT91SAM7A1 5 ...
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... NRESET is at logical 0. This allows external equipment to access the external memory devices (e.g., for Flash programming the application to add an external pull-up on the chip select lines in order to avoid EBI con- flicts at reset. 3. The EBI data bus D[15:0] has an internal pull-down. AT91SAM7A1 6 (1) (1) ...
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... Block Diagram Figure 4-1. AT91SAM7A1 Block Diagram I/O Power VDD5V Supply GND5V SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/MPIO PIO NPCS1/MPIO NPCS2/MPIO 2 PDC NPCS3/MPIO Channels RXD0/MPIO USART0 TXD0/MPIO PIO 2 PDC SCK0/MPIO Channels RXD1/MPIO USART1 TXD1/MPIO PIO 2 PDC SCK1/MPIO Channels RXD2/MPIO USART2 TXD2/MPIO PIO 2 PDC ...
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... To set the RTCKEN bit in the CM_CS register to logical 1, a write access to the CM_CE regis- ter must be done with a value of 0x23050080. To set the RTCKEN bit in the CM_CS register to logical 0, a write access to the CM_CD regis- ter must be done with a value of 0x18070080. AT91SAM7A1 8 6048B–ATARM–29-Jun-06 ...
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... Low frequency oscillator (32.768 kHz) is used as an internal system clock for core and all peripherals (CORECLK = RTCK, LFCLK = RTCK) The total power dissipation of the AT91SAM7A1 embedded system, when in low power mode, is estimated to be 170 µW maximum operating voltage of 3.3V, over the operating tem- perature range ...
Page 10
... The application must ensure a reset of at least allow time for the system clock to stabi- lize (CORECLK). The 32.768 kHz clock (RTCK) will be stabilized 300 ms after the reset is asserted. Software should not use or program the peripherals (WD, WT, ST) which are using this clock until it is stabilized. AT91SAM7A1 10 6048B–ATARM–29-Jun-06 ...
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... Electrical Characteristics Table 5-2. AT91SAM7A1 Pin Connections for 144-lead LQFP Package Pin Name Pad 1 D0 PC3B01D PC3B01D PC3B01D PC3B01D 40 5 VDD3V (I/O) 6 GND3V (I/O+CORE) 7 VDD3V (I/O+CORE PC3B01D 44 9 D10 PC3B01D PC3B01D 46 11 D11 PC3B01D PC3B01D 48 13 D12 PC3B01D PC3B01D 50 15 ...
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... Analog input pad Notes: 1. Differential (load-dependent) propagation delay, high-to-low or high impedance-to-low (V Slope = 1 ns) 2. Differential (load-dependent) propagation delay, low-to-high or high impedance-to-high (V Slope = 1 ns) 3. Propagation delay, high-to-low (V 4. Propagation delay, low-to-high (V AT91SAM7A1 12 (1) DTPDHL DTPDLH 0.144 ns/pF 0.131 ns/pF 0.072 ns/pF 0.066 ns/pF ...
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... TPDLH Pad Slope low to high transition Line Slope low to high transition Input Slope 50% high to low transition TPDHL Pad Slope high to low transition Line Slope high to low transition AT91SAM7A1 12, is the time in nano- Pad Line Capacitance (c) GND 50% DTPDLHxC 50% DTPDHLxC 50% 13 ...
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... Value of resistor RD depends on crystal frequency and manufacturer. Typical values of RD are given in Table 6-1. Signal MCKO RTCKO 6.2 Phase Locked Loop The AT91SAM7A1 microcontroller integrates a programmable PLL. The PLL requires an external RC network as described hereafter and in Figure 6-2. The optimum response with a simple RC filter is obtained when: Equation1: 0.4 AT91SAM7A1 14 ...
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... C 4 ------ ---------------------------------- - + the PLL input frequency (i.e., MCK). Conditions With ratio 1:1 AT91SAM7A1 6 Hz/V, min 65.10 Hz/V, max 172.10 . The value CKR ---------------------- - 5 Min Typ Max 0. 200 1:1 1:1024 65 ...
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... RTCP t 32.768kHz clock high time RTCH t 32.768kHz clock low time RTCL Dt Duty cycle (t /t RTCP RTCH RTCP Figure 6-4. RTCK AT91SAM7A1 16 Table 6-3. Master Clock Waveform t MH 0.7V VDD3V 0.3V VDD3V Minimum 0. 0. 32.768 kHz Clock Waveform t RTCH ...
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... These values are not characterized. 6048B–ATARM–29-Jun-06 Table Core Clock Waveform t CH 0.7V VDD3V VDD3V Conditions Crystal @ 4 MHz Crystal @ 4 MHz Crystal @ 8 MHz Fundamental @ 8 Mhz Fundamental @ 4 Mhz Crystal Crystal @ 4 MHz Crystal @ 4 MHz AT91SAM7A1 6-5. Minimum Maximum 32.768 40000 25 30517. ...
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... Startup time C1 Internal capacitance (RTCKI/GND) C2 Internal capacitance (RTCKO/GND) Equivalent load capacitance CL (RTCKI/RTCKO) DL Drive level Rs Series resistance Cs Shunt capacitance Load capacitance Cm Motional capacitance AT91SAM7A1 18 Conditions Min @ 32.768 kHz 40 Crystal Crystal 0.8 Crystal @ 32.768 kHz Crystal @ 32.768 kHz 1 Typ Max Unit 1.5 ...
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... Memory Map The AT91SAM7A1 microcontroller memory space is 4 Gbytes. When the AT91SAM7A1D microcontroller is reset, the ARM core is in reboot mode to access the external memory (usually a ROM) on NCS0 at address 0x00000000. The internal RAM is located at address 0x00300000. When the software execute the remap command (write 1 in RCB bit in AMC_RCR register), ...
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... Remap Mode Table 7-2. Memory Space 0xFFFFFFFF 0xFFDFFFFF AT91SAM7A1 20 Internal Memory (Remap Mode) Size 2 Mbytes 0xFFE00000 2046 Mbytes 0x80000000 0x7FFFFFFF 1024 Mbytes 0x40000000 0x3FFFFFFF 1021 Mbytes 0x00300000 0x002FFFFF 2 Mbytes 0x00100000 0x000FFFFF 1 Mbytes (4 Kbytes repeated 256 times) 0x00000000 Application Abort Generation ...
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... External Memories The AT91SAM7A1 external memories can be relocated in the address space from 0x40000000 to 0x7FFFFFFF. The configuration of the base address and the page size of each EBI chip select line (NCS[3:0], CS[7:6]) is done through the Advanced Memory Control- ler (AMC) registers noted that the two most significant bits of the base address are fixed to 01b allocat- ing these memories in the second of the four Gbytes memory spaces ...
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... Peripheral Resources The peripheral modules of the AT91SAM7A1 embedded system are listed in Table 7-4. Peripheral AMC SFM Watchdog Watch Timer USART0 USART1 USART2 SPI ADC0 (8-channel 10-bit) GPT0 (3 Channels) PWM (4 Channels) CAN (16 Channels) UPIO Capture CAPT0 Capture CAPT1 Simple Timer ST0 ...
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... Power Management Block In order to reduce power consumption, the AT91SAM7A1 microcontroller provides a power management block in some peripherals used to switch on/off the peripheral clocks (peripheral and PIO block). This function is independent of the Power Management Controller (peripheral) used to switch on/off the ARM7TDMI core and the PDC clocks. ...
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... PIO Controller Block Figure 9-1. To match different applications, the AT91SAM7A1 peripherals have their dedicated pins multi- plexed with general-purpose I/O pins (MPIO). Table 9-1 Table 9-1. Module AMC SFM Watchdog Watch Timer USART0 USART1 USART2 AT91SAM7A1 24 PIO Controller Block Diagram Pad Output Enable ...
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... Present Number of MPIO Yes No Yes Yes Yes Yes No Yes Yes Yes 22). shows the multiplexing of the peripheral signals with the PIO controller AT91SAM7A1 Name of PIO Lines 7 MISO, MOSI, SPCK, NPCS[3: TIOA0, TIOB0, TCLK0 3 TIOA1, TIOB1, TCLK1 3 TIOA2, TIOB2, TCLK2 4 PWM[3: UPIO[17:0] 1 CAPT0 ...
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... I/O as open drain or push pull. The multidriver option can be selected whether the I/O pin is controlled by the PIO controller or the peripheral controller. Bits at logical one in the PERIPHERAL_MDSR (Multidriver Status) indicate pins configured as open drain. AT91SAM7A1 26 6048B–ATARM–29-Jun-06 ...
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... The EBI is fully programmable through the Advanced Memory Controller (AMC) and can address Mbytes. It has up to six chip selects and a 22-bit address bus. The AT91SAM7A1 can only boot on a 16-bit external memory device connected to the NCS0 signal. All the other chip select lines (NCS[3:1] and CS[7:6]) can be configured to access 8- or 16-bit memory devices ...
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... The signal NWR1/NUB is not used • The signal NWR0/NWE is used as NWE and enables half-word writes. • The signal NRD/NOE is used as NOE and enables half-word reads. Figure 10-1. EBI Connection for External 16-bit Memory Device, 16-bit Access Only AT91SAM7A1 28 10-1. EBI ...
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... The signal NRD/NOE is used as NOE and enables half-word and byte reads. 6048B–ATARM–29-Jun-06 Figure 10-2 EBI D[15:0] A[21:1] NWE NOE NCS 10-3. AT91SAM7A1 shows how to connect 2 x 8-bit memory 8-bit External Memory (LSB) D[15:0] D[7:0] D[7:0] A[20:0] NWE NOE ...
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... Access Device Connection A typical 2 x 8-bit memory device connection with 8-bit or 16-bit access is shown in 5. • The signal A0/NLB is not used. • The signal NWR1/NUB is used as NWR1 and enables upper byte writes. AT91SAM7A1 30 EBI 16-bit External Memory D[15:0] ...
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... Access Device Connection A typical 16-bit memory device connection with 16-bit access only is shown in In this case, the AT91SAM7A1 is in byte write access mode and boots on the 16-bit memory. NWR1 and NWR0 are used by the EBI but only NWR0 is used by the memory, enabling a 16- bit access ...
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... Standard read protocol (default read mode) implements a read cycle in which NRD/NOE is active during the second half of the read cycle. The first half of the read cycle allows time to ensure completion of the previous access, as well as the output of address and NCS before the read cycle begins. AT91SAM7A1 32 EBI D[15:0] ...
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... NWE (or NWR0, NWR1) goes low only in the second half of the write cycle to avoid bus conflict. NWE (or NWR0, NWR1) goes high at the end of the write cycle unless wait states are asserted. 6048B–ATARM–29-Jun-06 Address Address Valid NCS NOE/NRD Address Address Valid NCS NOE/NRD AT91SAM7A1 33 ...
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... The read cycle is delayed one cycle for each wait state programmed. In early mode, NOE/NRD goes low at the start of the read cycle. In standard mode, this signal goes low at the half of the first cycle. Figure 10-11. Read Cycle with One Wait State AT91SAM7A1 34 Address Address Valid ...
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... Data float wait states are asserted between accesses. 6048B–ATARM–29-Jun-06 Address NCS Address NCS NWE Address NCS ) for each external memory device is programmed in the TDF DF AT91SAM7A1 Address Valid Address Valid Address Valid 35 ...
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... NCSy Write NCSx Write NCSy Read NCSx Write NCSy Write Illustrations from description of how data float wait states apply. AT91SAM7A1 36 describes the data float wait states applied between external access cycles. Data Float States Applied Next Access NCSx Read NCSx Write ...
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... Data Float Address 1 NCS 1 NCS 2 NWE Data Read Mem 1 Read Data Float Address 1 NCS NWE Data Read Data 1 AT91SAM7A1 Data Float Write Mem 2 Data Float Address 2 Write Mem 2 NTDF = 2 Data Float Write Mem 2 Address 2 Write Mem 2 Data Float Write Address 2 Write Data 2 ...
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... Figure 10-18. Sequential Early Read Access on the Same Chip Select with One Wait State ADDRESS NOE/NRD Figure 10-19. Sequential Early Read Access on the Same Chip Select with No Wait State Figure 10-20. Sequential Read Access on Different Chip Select with NTDF = 2 ADDRESS NOE/NRD AT91SAM7A1 38 Read Address 1 NCS Data Data 1 ...
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... Address 1 NCS Data Data1 Read ADDRESS Address 1 Address 2 NCS NOE/NRD Data Data 1 Read Address 1 NCS NWE Data Data 1 AT91SAM7A1 Data Float Read Mem 2 Data Float Address 2 Read Mem 2 Read Address 2 Data 2 Read Read Data Float Address 3 Data 2 Data 3 Write Address 2 Data 2 ...
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... Figure 10-25. Sequential Write Access on the Same Chip Select with No Wait State Figure 10-26. Sequential Write Access on Different Chip Select Figure 10-27. Write and Early Read on the Same Chip Select AT91SAM7A1 40 Write Write Address 1 Address 2 ADDRESS NCS NWE Data Data 1 Write Mem 1 ...
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... Write Mem 1 Write ADDRESS Address 1 NCS NOE/NRD NWE Data 47. 0 NWS WSCSAWSL (Figure 10-32). AT91SAM7A1 Data Float Read Mem 2 Data Float Address 2 Read Mem 2 Read Data Float Address 2 Write Data 1 Read Data 2 Table 10-5, “Timings for External NWAIT,” on load_delay t – CYCLE ...
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... Figure 10-30. External Accesses with 0 Internal Wait States and no NWAIT CORECLK NCS Address NOE/NRD NWE NWAIT Figure 10-31. External Accesses with 0 Internal Wait States and NWAIT Detected CORECLK NCS Address NOE/NRD NWE NWAIT AT91SAM7A1 42 6048B–ATARM–29-Jun-06 ...
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... NWAIT input correctly (t respected). Figure 10-33. External Accesses with One Internal Wait State and One NWAIT CORECLK NCS Address NOE/NRD NWE NWAIT 6048B–ATARM–29-Jun-06 AT91SAM7A1 WSADCWSL WSCSAWSL and t must be WSPL 43 ...
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... Output enable low to read data valid tr OELRDV2 (early read) Byte select low to read data valid tr (read/write memory, 0 wait state, BSLRDV2 standard read) Byte select low to read data valid tr BSLRDV1 (all other cases) AT91SAM7A1 44 Load = 15pf Load = 40pf Min Max Min t - CYCLE 19.2ns (1 + NWS NWS) * ...
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... Max 0 -1.5ns 0 CYCLE 1.5ns 0 CYCLE 2.8ns 4.8ns tr ADCRDV 1/2 Address Valid tr CSLRDV DHZCSL tr BSLRDV 1/2 tr OELRDV1 (standard) tr OELRDV2 (early) DHZOEL2 tr DHZOEL1 AT91SAM7A1 Load = 40pf Load = 60pf Min Max Min 0 0 -3.4ns -4.8ns 0 CYCLE CYCLE 3.4ns 4.8ns 0 CYCLE CYCLE 4.7ns 6 ...
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... Chip select high (previous is a read tw CSHDD cycle) to data drive Data hold time from write high (one tw DHWH1 or more wait states) Data hold time from write high (0 wait tw DHWH2 state) AT91SAM7A1 46 Load = 15pf Load = 40pf Min Max Min 0 0 CYCLE CYCLE 2 ...
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... Max (0.5 + NWS CYCLE 16.8ns (0.5 + NWS CYCLE 15.8ns t t CYCLE CYCLE CYCLE tw SADCWSL tw SCSAWSL tw SPL AT91SAM7A1 tw ADHWH 1/2 tw DHWH 1/2 Data Out Valid Load = 40pf Load = 60pf Min Max Min (0.5 + NWS CYCLE 23.5ns (0.5 + NWS CYCLE 22.5ns t CYCLE CYCLE ...
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... EBI25 EBI26 EBI13 EBI23 EBI14 EBI15 EBI16 EBI17 EBI18 Note: AT91SAM7A1 48 and Table 10-7 show estimated timings relative to operating condition limits (worst General-purpose EBI Signals Parameter CORECLK falling to NCS, CS active CORECLK falling to NCS, CS inactive CORECLK falling to A[21:0] active CORECLK falling to A[21:0] inactive ...
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... EBI 1 no wait EBI EBI EBI EBI 14 EBI 15 EBI 8 EBI EBI 9 EBI 12 EBI Derating Factor TPDHL = + X EBI Derating Factor TPDLH = + X AT91SAM7A1 EBI 24 EBI 2 wait EBI 26 EBI 17 23 EBI 15 EBI 16 EBI 19 EBI EBI 11 10 EBI EBI EBI wait wait DTPDHL C TPDHL + – ...
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... DTPDLH is differential (load-dependent) propagation delay, low-to-high or high impedance- to-high • C NEW • the current capacitive charge on the signal (40 pF load for all signals except for chip select lines - 15pF -) AT91SAM7A1 50 is the new capacitive charge on the affected signal 6048B–ATARM–29-Jun-06 ...
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... AMC Memory Control Register Note: 1. The software must set the AMC Registers for correct operation. 6048B–ATARM–29-Jun-06 (1) Name AMC_CSR0 AMC_CSR1 AMC_CSR2 AMC_CSR3 --- AMC_CSR6 AMC_CSR7 AMC_RCR AMC_MCR AT91SAM7A1 Access Reset State Read/Write 0x4000203D Read/Write 0x48000000 Read/Write 0x50000000 Read/Write 0x58000000 --- --- Read/Write 0x70000000 ...
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... CSEN: Chip Select Enable 0: Chip select is disabled. 1: Chip select is enabled. • BAT: Byte Access Type 0: Byte write access type. 1: Byte select access type. • TDF[2:0]: Data Float Output Time These bits select the number of cycles added after a memory transfer. TDF[2: AT91SAM7A1 – CSEN BAT ...
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... DBW[1:0]: Data Bus Width Type of data bus selected. DBW[1: 6048B–ATARM–29-Jun-06 Page Size 0 1 Mbytes 1 4 Mbytes 0 16 Mbytes 1 64 Mbytes NWS[2: AT91SAM7A1 Active Bits in Base Address 12 (31-20) 10 (31-22) 8 (31-24) 6 (31-26) WS Added Data Bus Width Reserved 16-bit Data Bus 8-bit Data Bus Reserved 53 ...
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... CSEN: Chip Select Enable 0: Chip select is disabled. 1: Chip select is enabled. • BAT: Byte Access Type 0: Byte write access type. 1: Byte select access type. • TDF[2:0]: Data Float Output Time These bits select the number of cycles added after a memory transfer. TDF[2: AT91SAM7A1 – CSEN BAT ...
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... DBW[1:0]: Data Bus Width Type of data bus selected 6048B–ATARM–29-Jun-06 Page Size 0 1 Mbytes 1 4 Mbytes 0 16 Mbytes 1 64 Mbytes DBW[1: AT91SAM7A1 Active Bits in Base Address 12 (31-20) 10 (31-22) 8 (31-24) 6 (31-26) WS Added Data Bus Width Reserved 16-bit Data Bus 8-bit Data Bus Reserved 55 ...
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... Reset value for CSEN is 0, A21/CS6 and A20/CS7 are configured as address lines after reset. • BAT: Byte Access Type 0: Byte write access type. 1: Byte select access type. • TDF[2:0]: Data Float Output Time These bits select the number of cycles added after a memory transfer. TDF[2: AT91SAM7A1 – CSEN BAT 5 ...
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... DBW[1:0]: Data Bus Width Type of data bus selected 6048B–ATARM–29-Jun-06 Page Size 0 1 Mbytes 1 4 Mbytes 0 16 Mbytes 1 64 Mbytes DBW[1: AT91SAM7A1 Active Bits in Base Address 12 (31-20) 10 (31-22) 8 (31-24) 6 (31-26) WS Added Data Bus Width Reserved 16-bit Data Bus 8-bit Data Bus Reserved 57 ...
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... RCB: Remap Command Bit 0: No effect 1: Performs the remapping of the two memory devices (internal RAM and external memory on NCS0). Memory map switches from 'reboot' mode to 'remap mode'. This bit is read at logical 0 in reboot mode and at logical 1 in remap mode. AT91SAM7A1 – ...
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... DRP – Maximum Addressable Space Valid Address Bits per Chip Select Line ADD[21:0] ADD[21:0] ADD[20:0] ADD[19:0] AT91SAM7A1 26 25 – – – – – – ALE[2:0] Valid Chip Select 4 Mbytes NCS[3:0] 4 Mbytes NCS[3:0] 2 Mbytes NCS[3:0], CS6 ...
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... Clock Manager (CM) The AT91SAM7A1 microcontroller provides: • 32.768 kHz oscillator (real-time clock oscillator) • 4 MHz to 16 MHz oscillator • Programmable PLL (x2 to x20) • Programmable master clock divider Clock management is done through the Clock Manager (CM). This allows the user to select between the different working modes LPM, SLM and OPE. ...
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... CM_C CM_C PLLSL PLLDI MCKE PLLE AT91SAM7A1 CM_CS CM_CS 13 14 RTCSL DIVEN CT CORECLK MCK (2x(MDIV+ MCK 1 0 MCKxPMUL (MCKxPMUL RTCK MCK (2x(MDIV+ MCK 0 1 MCKxPMUL (MCKxPMUL MCK (2x(MDIV+1) ) MCK (2x(MDIV+ MCK 1 0 MCKxPMUL (MCKxPMUL 1 0 )/2 LFCLK Mode MCK/ SLM (2x(MDIV+ 1)) ...
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... Address Register 0xFFFEC000 CM Clock Enable 0xFFFEC004 CM Clock Disable 0xFFFEC008 CM Clock Status 0xFFFEC00C CM PLL Stabilization Time 0xFFFEC010 CM PLL Divider 0xFFFEC014 CM Oscillator Stabilization Time 0xFFFEC018 CM Master Clock Divider AT91SAM7A1 62 Name Access CM_CE Write-only CM_CD Write-only CM_CS Read-only CM_PST Read/Write CM_PDIV Read/Write CM_OST Read/Write ...
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... CLKDKEY[15:0]: Key for Write Access into the CM_CD Register Any write in the CM_CD register bits will be effective only if CLKDKEY[15:0] is equal to 0x1807. 6048B–ATARM–29-Jun- CLKEKEY[15: CLKEKEY[7: – – DIVSLCT – LFSLCT 29 28 CLKDKEY[15: CLKDKEY[7: – – DIVSLCT – LFSLCT AT91SAM7A1 – – – PLLSLCT – – – – PLLSLCT – ...
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... MCKEN: Master Clock Oscillator Enable 0: MCKEN signal logical 0. The master clock oscillator is disabled and bypassed. 1: MCKEN signal logical 1. The master clock oscillator is activated. • PLLEN: PLL Enable 0: PLLEN signal logical 0. PLL is deactivated. 1: PLLEN signal logical 1. PLL is enabled. AT91SAM7A1 – – ...
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... DIVEN: Programmable Divider Enable 0: DIVEN signal logical 0. The programmable divider is disabled. 1: DIVEN signal logical 1. The programmable divider is enabled. • RTCSLCT: Low Frequency Clock Selection 0: RTCSLCT signal logical 0. The DIVCLK is selected for LFCLK. 1: RTCSLCT signal logical 1. The RTCK is selected for LFCLK. 6048B–ATARM–29-Jun-06 AT91SAM7A1 65 ...
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... PSTKEY[15:0]: Key for Write Access into the CM_PST Register Any write in PSTB[9:0] are effective only if PSTKEY[15:0] is equal to 0x59C1. These bits are always read at 0. Note: Write accesses to this register are only valid if PLLEN is at logical 0 (i.e., PLL not enabled). AT91SAM7A1 ...
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... The output frequency of the PLL is equal to: MCK x PMUL[4:0], where MCK is the PLL input clock. Note: Write accesses to this register are only valid if PLLEN is at logical 0 (i.e., PLL disabled). 6048B–ATARM–29-Jun- PDIVKEY[15: PDIVKEY[7: – – – – AT91SAM7A1 – – PMUL[4:0] PLL Multiplier Remains in previous state (1) Remains in previous state 2 3 … Remains in previous state ...
Page 68
... The default value is 0x000000B0 guaranteeing 176 x 256 MCK clock cycles (i.e., 11.264 ms with MCK = 4.0 MHz) • OSTKEY[15:0]: Key for Write Access into the CM_OST Register Any write in the OSTB[9:0] bits will only be effective if the OSTKEY[15:0] bits are equal to 0xDB5A. These bits are always read at 0. AT91SAM7A1 ...
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... MDIVKEY[15:0]: Key for Write Access into the CM_MDIV Register Any write in the MDIV[6:0] bits is effective only if the MDIVKEY[15:0] bits are equal to 0xACDC. These bits are always read at 0. 6048B–ATARM–29-Jun- MDIVKEY[15: MDIVKEY[7: – – – MDIV[6: AT91SAM7A1 – – – ...
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... Test Mode The AT91SAM7A1 provides functional test mode in order to check or test some registers in internal peripherals. The test mode is entered using the SFM_TM register. It must be noted that this test mode is different from the factory test mode entered through the external pins TEST and SCANEN ...
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... SFM Memory Map Address Register 0xFFF00000 SFM Chip ID 0xFFF00004 SFM Extended Chip ID 0xFFF00008 SFM Reset Status 0xFFF0000C Reserved 0xFFF00014 SFM Test Mode 6048B–ATARM–29-Jun-06 Name SFM_CIDR SFM_EXID SFM_RSR --- SFM_TM AT91SAM7A1 Access Reset State Read-only 0x80000300 Read-only 0x02001102 0x0000006C Read-only or 0x00000053 --- --- Read/Write 0x00000000 71 ...
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... Internal RAM size = 2 bytes. • NVPMT[3:0]: Non Volatile Program Memory Type 0000 : ROMless. b 0001 : Mask ROM. b Other: Reserved. • ARCH[3:0]: Core Architecture 0000 : ARM7TDMI. b Other: Reserved. • EXT: Extension Flag 0: No extended chip ID. 1: Extended chip ID existing. AT91SAM7A1 – – – bytes. ...
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... This register gives the last cause of reset. • RESET[7:0]: Cause of Reset 0x6C: External reset on NRESET pin. 0x53: Internal watchdog reset. 6048B–ATARM–29-Jun- – – – – – – – – – RESET[7:0] AT91SAM7A1 – – – – – – ...
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... Disable test mode (the internal TEST_ENABLE signal is driven low at peripherals input). 1: Enable test mode (the internal TEST_ENABLE signal is driven high at peripherals input). • KEY[15:0]: Test Key for Test Mode Entry TESTEN bit can only be set/reset if the correct KEY word is entered: KEY[15:0] = 0xD64A. AT91SAM7A1 ...
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... To update the contents of the mode and control registers necessary to write the correct bit pattern to the control access key bits at the same time as the control bits are written (the same write access). 6048B–ATARM–29-Jun-06 WD Counter Clock Dividers WDSCLK WDPIDCLK 0 LFCLK 1 CORECLK SYSCAL[10:0]divider AT91SAM7A1 WDCLK LFCLK LFCLK WDPDIV[2:0]divider CORECLK CORECLK SYSCAL[10:0]divider x WDPDIV[2:0]divider 75 ...
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... reset is programmed (i.e., RSTEN logical 0) when the WD reaches reset to the programmed value and continues to count, unless it is disabled. This enables it to gen- erate periodic interrupts. Figure 13-1. Watchdog Block Diagram CORECLK 1 Programmable Divider 0 LFCLK (SYSCAL) WD_MR SYSCAL[10:0] WD_MR.3 SYSCLK AT91SAM7A1 76 11 HPCV 0xFFF 1 WDCLK freq 11 HPCV ...
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... LFCLK/8 101b LFCLK/128 111b LFCLK/1024 WDPDIVCLK WDPDIV[2:0] CORECLK 000b CORECLK/2 001b CORECLK/512 010b CORECLK/1610 101b CORECLK/4094 111b AT91SAM7A1 Time to WD Overflow 0.109 s 0.125 s 0.468 s 0.500 s 1.437 s 1.500 s 175 s 176 s 1040 s 2048 s Time to WD WDCLK Pending WDPDIVCLK/2 119.4 µs WDPDIVCLK/4 1.024 ms WDPDIVCLK/8 803 ...
Page 78
... Interrupt Disable Register 0xFFFA007C Interrupt Mask Register 0xFFFA0080 Test Register 0xFFFA0084 Counter Test Register 0xFFFA0088 Preload Test Register Note: 1. The reset value of this register depends on the level of the external pin at reset. AT91SAM7A1 78 Name Access --- --- WD_CR Write-only WD_MR Read/Write WD_OMR Read/Write ...
Page 79
... RSTKEY[15:0]: Restart Key 0xC071: Watchdog counter is restarted if its value is equal or less than 0x00FF (PENDING = 1 in WD_SR). Other value: No effect. 6048B–ATARM–29-Jun- – – – – – – RSTKEY[15: RSTKEY[7:0] AT91SAM7A1 – – – – – – ...
Page 80
... WDSCLK = LFCLK 1: WDSCLK = CORECLK • SYSCAL[10:0]: System Clock Prescalar Value This prescalar is used to divide the WDSCLK clock when system clock is selected (SYSCLK = 1). 0x000: WDPDIVCLK = CORECLK Other value: WDPDIVCLK A write in this field can only be done when system clock is not selected (SYSCLK = 0). AT91SAM7A1 CKEY[7: – ...
Page 81
... Counter is preloaded when watchdog counter is restarted with bits set to 0x7FF and bits equal to HPCV[4:0] (i.e., the counter value is (HPCV[4: • CKEY[7:0]: Clock Access Key Used only when writing in WD_MR. CKEY is read as 0. Write access in WD_MR is allowed only if CKEY[7:0] = 0x37. 6048B–ATARM–29-Jun- 0x7FF). AT91SAM7A1 81 ...
Page 82
... Generation of an internal reset by the Watchdog is disabled. 1: When overflow occurs, the Watchdog generates an internal reset. • OKEY[11:0]: Overflow Access Key Used only when writing WD_OMR. OKEY is read as 0. 0x234: Write access in WD_OMR is allowed. Other value: Write access in WD_OMR is prohibited. AT91SAM7A1 – ...
Page 83
... Clear Watchdog pending interrupt. • WDOVF: Watchdog Overflow Clear 0: No effect. 1: Clear Watchdog overflow interrupt. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – – – – – – – – WDOVF WDPEND 83 ...
Page 84
... WDPEND: Watchdog Pending 0: No Watchdog pending Watchdog pending has occurred. • WDOVF: Watchdog Overflow 0: No Watchdog overflow Watchdog overflow has occurred. • PENDING: Watchdog Pending Status 0: Watchdog counter is over 0x00FF (not pending). 1: Watchdog is pending window (between 0x00FF and 0x0000). AT91SAM7A1 – – – 21 ...
Page 85
... AT91SAM7A1 – – – – – – – – – – WDOVF WDPEND – – – – – – – ...
Page 86
... WDPEND: Watchdog Pending Interrupt Mask 0: The WDPEND interrupt is disabled. 1: The WDPEND interrupt is enabled. • WDOVF: Watchdog Overflow Interrupt Mask 0: The WDOVF interrupt is disabled. 1: The WDOVF interrupt is enabled. AT91SAM7A1 – – – – – – – ...
Page 87
... Writing to this register has no effect, it does not change the value which is read. This bit is reset when a reset timeout occurs. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – – – – – – – WDIV WDRV TMEN 87 ...
Page 88
... As the watchdog counter is asynchronous, the write of the right key in WD_CR does not immediately set the watchdog value to initial value. During this delay, this bit is set to one (between reset command and real reset of the counter). For the same reason, this register must be read twice to be sure of the value. AT91SAM7A1 88 29 ...
Page 89
... This register is used to preload the initial value of the counter in test mode not readable (if a read is attempted the value is undefined) and it can only be accessed in test mode. After reset, CTPR[15:0] is initialized to 0x0FFF. 6048B–ATARM–29-Jun- – – – – – – CTPR[15: CTPR[7:0] AT91SAM7A1 – – – – – – ...
Page 90
... CAN Time Stamp The 32-bit register that forms the seconds counter is provided to the CAN module. After each transmission or reception of a CAN frame, the value of the current seconds counter is auto- matically written in the corresponding CAN channel CAN_STPx register. AT91SAM7A1 90 ”Asynchronous Interface” on page 90). ...
Page 91
... Reserved 0xFFFA406C Clear Status Register 0xFFFA4070 Status Register 0xFFFA4074 Interrupt Enable Register 0xFFFA4078 Interrupt Disable Register 0xFFFA407C Interrupt Mask Register 0xFFFA4080 Seconds Register 0xFFFA4084 Alarm Register 6048B–ATARM–29-Jun-06 AT91SAM7A1 Name Access --- --- WT_CR Write-only WT_MR Read/Write --- --- WT_CSR Write-only WT_SR Read-only WT_IER ...
Page 92
... In case both SECSEN and SECSDIS are equal to one when the control register is written, the WT seconds counter is disabled. • ALARMEN: WT Alarm Enable 0: No effect. 1: Enables the WT alarm. • ALARMDIS: WT Alarm Disable 0: No effect. 1: Disables the WT alarm. In case both ALARMEN and ALARMDIS are equal to one when the control register is written, the WT alarm is disabled. AT91SAM7A1 – – – 21 ...
Page 93
... The seconds counter is reset to 0x00000000 at the end of the period when it reaches 0xA8BFFFFF. 1: The seconds counter is reset to 0x00000000 at the end of the period when it reaches 0xFFFFFFFF. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – – – – – – – – – SECRST 93 ...
Page 94
... SECSDIS: Clear Seconds Counter Disabled 0: No effect. 1: Clear the seconds counter disabled interrupt. • ALARMEN: Clear Alarm Enabled 0: No effect. 1: Clear the alarm enabled interrupt. • ALARMDIS: Clear Alarm Disabled 0: No effect. 1: Clear the alarm disabled interrupt. AT91SAM7A1 – – – 21 ...
Page 95
... Seconds counter is enabled. • ALARMENS: Alarm Enable Status 0: Alarm is disabled. 1: Alarm is enabled. 6048B–ATARM–29-Jun- – – – – – – – – – WSEC ALARMDIS ALARMEN AT91SAM7A1 26 25 – – – – – ALARMENS SECENS 2 1 SECSDIS SECSEN ALARM 24 – 16 – ...
Page 96
... WT Interrupt Disable Register Name: WT_IMR Access: Write-only Address: 0xFFFA4078 31 30 – – – – – – – – AT91SAM7A1 – – – – – – – – – – ALARMDIS ALARMEN – – – – ...
Page 97
... ALARMDIS: Alarm Disabled Interrupt Mask 0: ALARMDIS interrupt is disabled. 1: ALARMDIS interrupt is enabled. 6048B–ATARM–29-Jun- – – – – – – – – – – ALARMDIS ALARMEN AT91SAM7A1 26 25 – – – – – – SECSDIS SECSEN ALARM 24 – 16 – 8 – ...
Page 98
... ALARMREG[31:0]: Alarm Register An interrupt can be generated when the seconds register reaches this value. This register can only be written when ALARMENS = 0. An invalid data (i.e., value greater than or equal to 0xA8C00000) is not written into the alarm register if in 24-hour mode. AT91SAM7A1 SECONDS[31:24] ...
Page 99
... The peripherals that are associated to PDC channel are listed in 6048B–ATARM–29-Jun-06 Arbiter PDC CH9 CH8 CH7 CH6 CH5 PDC PDC CAPT0 SPI AT91SAM7A1 ARM7TDMI Core RAM ASB AMBA Bridge APB CH4 CH3 CH2 CH1 PDC PDC ...
Page 100
... When a transfer is performed, the counter is decremented and the pointer is incremented. When the counter reaches 0 (i.e., all the data have been sent/receive to/from the module), the end status bit is set in peripheral status register and can be programmed to generate an interrupt. AT91SAM7A1 100 Memory Memory ...
Page 101
... Memory Pointer There is one 32-bit memory address pointer for each channel (PDC_MPRx). Each memory pointer points to a location in the AT91SAM7A1 memory space (on chip RAM or external memory on the EBI). The PDC_MPRx is automatically incremented after each transfer, for byte, half- word or word transfers. The PDC_MPRx must be initialized before any transfers are started. ...
Page 102
... For emulation purposes, each PDC channel can be software configured to be attached to a different peripheral. In the AT91SAM7A1 microcontroller, each PDC channel is attached to a dedicated peripheral (with a fixed direction and fixed address). Software must configure each PDC channel so the accesses are correctly done by the PDC module: Table 15-1 ...
Page 103
... RX: Ch4 Reception USART2_SR TX: Ch5 Transmission USART2_SR RX: Ch6 Reception TX: Ch7 Transmission Ch8 Reception CAPT0_SR Ch9 Reception CAPT1_SR Ch10 Reception AT91SAM7A1 End of Transfer Bit in Status Register ENDRX ENDTX ENDRX ENDTX ENDRX ENDTX SPI_SR REND SPI_SR TEND PDCEND PDCEND ADC_SR TEND Status Bit for ...
Page 104
... When all the 8-bit words have been received (i.e., all bytes have been written in external RAM), the REND bit in the SPI_SR register will be set to a logical 1 informing the software that the transfer is completed. The REND bit in the SPI_SR register can also generate an interrupt if the corresponding bit is set in the SPI_IMR register. AT91SAM7A1 104 6048B–ATARM–29-Jun-06 ...
Page 105
... CH6 Control Register 0xFFFF80E8 CH6 Memory Pointer 0xFFFF80EC CH6 Transfer Counter 0xFFFF80F0 CH7 Peripheral Register Address 0xFFFF80F4 CH7 Control Register 0xFFFF80F8 CH7 Memory Pointer 0xFFFF80FC CH7 Transfer Counter 6048B–ATARM–29-Jun-06 AT91SAM7A1 Name Access --- --- PDC_PRA0 Read/Write PDC_CR0 Read/Write PDC_MPR0 Read/Write PDC_TCR0 Read/Write PDC_PRA1 ...
Page 106
... CH9 Transfer Counter 0xFFFF8120 CH10 Peripheral Register Address 0xFFFF8124 CH10 Control Register 0xFFFF8128 CH10 Memory Pointer 0xFFFF812C CH10 Transfer Counter 0xFFFF8130 – Reserved 0xFFFF8EEC 0xFFFF8F00 Test Register AT91SAM7A1 106 Name Access PDC_PRA8 Read/Write PDC_CR8 Read/Write PDC_MPR8 Read/Write PDC_TCR8 Read/Write PDC_PRA9 Read/Write PDC_CR9 ...
Page 107
... PDC CHx Peripheral Register Address Name: PDC_PRAx Access: Read/Write Address: 0xFFFF8XX0 • CHPRA[31:0] Peripheral Register Address CHPRA[31:0] must be loaded with the address of the target register (peripheral receive or transmit register). 6048B–ATARM–29-Jun- CHPRA[31:24 CHPRA[23:16 CHPRA[15: CHPRA[7:0] AT91SAM7A1 107 ...
Page 108
... DIR: Transfer Direction 0: Peripheral to memory. 1: Memory to peripheral. • SIZE[1:0]: Transfer Size Defines the size of the transfer AT91SAM7A1 108 – – – – – – – – – – – – ...
Page 109
... CHCTR[15:0] must be loaded with the size of the receive buffer. 0: Stop Peripheral Data Transfer dedicated to the peripheral 65535: Start immediately Peripheral Data Transfer. 6048B–ATARM–29-Jun- CHPTR[31:24 CHPTR[23:16 CHPTR[15: CHPTR[7: – – – – – – CHCTR[15: CHCTR[7:0] AT91SAM7A1 – – – – – – 109 ...
Page 110
... TCH7 TCH6 • TCHx: Trigger Channel x This register is only valid in test mode (see SFM register) and used to emulate a transfer trigger effect. 1: Triggers a transfer on channel x. AT91SAM7A1 110 – – – – – – – – – ...
Page 111
... External Interrupt FIQ Interrupt Sources Interrupt Source 0 1 Software interrupt Software interrupt 1 9 Software interrupt Software interrupt 3 AT91SAM7A1 Figure 16-1. The processor’s IRQ ARM7TDMI GIC Core FIQ ASB AMBA Bridge APB Description Fast interrupt Watchdog Watch Timer USART0 USART1 USART2 ...
Page 112
... The value read in the GIC_IVR corresponds to the address stored in the Source Vector Register (GIC_SVR) of the current interrupt. Each interrupt source has its cor- responding GIC_SVR. In order to take advantage of the hardware interrupt vectoring necessary to store the address of each interrupt handler in the corresponding GIC_SVR at system initialization. AT91SAM7A1 112 Interrupt Sources (Continued) Description 12 ...
Page 113
... At the end of the interrupt service routine, the end of interrupt command register (GIC_EOICR) must be written. This allows pending interrupts to be serviced. 6048B–ATARM–29-Jun-06 0xFFFFF104 GIC_FVR 0xFFFFF100 GIC_IVR Index Table 16-1 on page AT91SAM7A1 @ of interrupt subroutine 31 GIC_SVT31 GIC_SVR30 ... @ of interrupt GIC_SVR2 subroutine 0 GIC_SVR1 ...
Page 114
... The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded 2. The ARM core enters IRQ mode not already. 3. When the instruction loaded at address 0x18 is executed, the Program Counter is AT91SAM7A1 114 ldr PC,[PC,# -&F20] in the IRQ link register (r14_irq) and the Program Counter (r15) is loaded with 0x18. ...
Page 115
... ARM core). The I bit in the SPSR is significant set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is completed (IRQ is masked). AT91SAM7A1 115 ...
Page 116
... The Spurious Interrupt Routine must at least write into the GIC_EOICR to perform an 5. This causes the ARM7TDMI to jump into the Spurious Interrupt Routine. 6. During a Spurious Interrupt Routine, the Interrupt Status Register GIC_ISR reads 0. AT91SAM7A1 116 in the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded with 0x1C. ...
Page 117
... GIC_SMR31 GIC_SVR0 – Read/Write GIC_SVR31 GIC_IVR Read-only GIC_FVR Read-only GIC_ISR Read-only GIC_IPR Read-only GIC_IMR Read-only GIC_CISR Read-only --- --- GIC_IECR Write-only GIC_IDCR Write-only GIC_ICCR Write-only GIC_ISCR Write-only GIC_EOICR Write-only GIC_SPU Read/Write AT91SAM7A1 Reset State 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 --- 0x00000000 0x00000000 --- --- --- --- --- --- 0x00000000 117 ...
Page 118
... These bits program the priority level (from 0-lowest to 7-highest) of all the interrupt sources. The priority level is not used for the FIQ in the SMR0. • SRCTYP[1:0]: Interrupt Source Type (1) SRCTYP[1: Note: 1. All the interrupts used by internal peripherals are considered as internal interrupts and subsequently the SRCTYP1 bit is always read at 0. AT91SAM7A1 118 – – – – – – – ...
Page 119
... Access: Read-only Address: 0xFFFFF100 • IRQV[31:0]: Interrupt Vector Address Address of the currently serviced interrupt vector (user programmed in the GIC_SVR register). Note: GIC_IVR = 0x00000000 when there is no current interrupt. 6048B–ATARM–29-Jun- VECT[31:24 VECT[23:16 VECT[15: VECT[7: IRQV[31:24 IRQV[23:16 IRQV[15: IRQV[7:0] AT91SAM7A1 119 ...
Page 120
... Address of the FIQ serviced interrupt (user programmed in the GIC_SVR0 register). 16.5.5 GIC Interrupt Status Register Name: GIC_ISR Access: Read-only Address: 0xFFFFF108 31 30 – – – – – – – – • IRQID[4:0]: Current IRQ Identifier Current interrupt source number. AT91SAM7A1 120 FIQV[31:24 FIQV[23:16 FIQV[15: FIQV[7: – – – – ...
Page 121
... GPT0CH2 GPT0CH1 7 6 SPI USART2 • Interrupt Pending 0: Corresponding interrupt is inactive. 1: Corresponding interrupt is pending. 6048B–ATARM–29-Jun- SWIRQ10 IRQ0 SWIRQ9 21 20 UPIO CAN SWIRQ7 13 12 GPT0CH0 SWIRQ3 5 4 USART1 USART0 AT91SAM7A1 SWIRQ8 ST1 SWIRQ6 SWIRQ5 ADC0 SWIRQ2 SWIRQ0 24 ST0 16 PWM 8 SWIRQ1 ...
Page 122
... GIC Interrupt Enable Command Register Name: GIC_IECR Access: Write-only Address: 0xFFFFF120 31 30 SWIRQ7 SWIRQ6 23 22 CAPT1 CAPT0 15 14 SWIRQ1 GPT0CH2 GPT0CH1 7 6 SPI CAN3 USART1 AT91SAM7A1 122 – – – – – – – – – – – – 29 ...
Page 123
... UPIO CAN0 PWM GPT0CH0 ADC1 5 4 USART1 USART0 IRQ1 IRQ0 SWIRQ5 UPIO CAN0 PWM GPT0CH0 ADC1 5 4 USART1 USART0 WT AT91SAM7A1 26 25 SWIRQ4 ST1 18 17 GPT1CH0 SWIRQ3 10 9 ADC0 CAN2 SWIRQ0 26 25 SWIRQ4 ST1 18 17 GPT1CH0 SWIRQ3 10 9 ADC0 CAN2 SWIRQ0 24 ST0 ...
Page 124
... Name: GIC_ICSR Access: Write-only Address: 0xFFFFF12C 31 30 SWIRQ7 SWIRQ6 23 22 CAPT1 CAPT0 15 14 SWIRQ1 GPT0CH2 GPT0CH1 7 6 SPI CAN3 USART1 • Software Interrupt Set 0: No effect. 1: Sets corresponding software interrupt. AT91SAM7A1 124 IRQ1 IRQ0 SWIRQ5 UPIO CAN0 PWM GPT0CH0 ADC1 USART0 ...
Page 125
... SPUVECT[31:0]: Spurious Interrupt Vector Handler Address Address of the spurious interrupt handler. 6048B–ATARM–29-Jun- – – – – – – – – – – – – SPUVECT[31:24 SPUVECT[23:16 SPUVECT[15: SPUVECT[7:0] AT91SAM7A1 – – – – – – – – – – – – 125 ...
Page 126
... However, both voltage references must be separated by a minimum of 2.4V (i.e., VREFP must be greater than 2.4V according to GNDANA). AT91SAM7A1 126 a. By the microprocessor, by setting the STOP bit of the active control register the PDC: TEND can stop the conversion if the STOPEN bit of the mode regis- ter is active ...
Page 127
... D[9:0]. The End of Conversion signal (EOC) is set high. The input is sampled again as the hold signal goes low and a new conversion can be started with a high-pulse of the start signal. 6048B–ATARM–29-Jun- AT91SAM7A1 9 Data Valid 127 ...
Page 128
... ADC Mode Register (ADC_MR). The master clock is divided by this value, and the result is the ADC clock. The preload value is coded on 7 bits with the 2 LSBs always low to guarantee a duty cycle of ½. The user divides AT91SAM7A1 128 ADC_MR.10 ADC_MR ...
Page 129
... STOPEN is active. The digital interface between the analog part and the APB bus is in standa- lone mode; this permits conversion without any help. This mode can be associated with multiple conversion as well as single conversion. The different steps of the conversion are equivalent to those of a single conversion. 6048B–ATARM–29-Jun-06 AT91SAM7A1 129 ...
Page 130
... These bits indicate how many inputs are considered by the peripheral for conversion. CONT Mode The CONTCV bit of the ADC Mode Register indicates if the peripheral is converting in a con- tinuous mode (in this case the bit is high) or not. This bit is initialized to 0. AT91SAM7A1 130 6048B–ATARM–29-Jun-06 ...
Page 131
... EOC bit in ADC_SR. Another result can be saved before the data has been read. In this case, the OVR bit is set. When the PDC has stored all the data required, the TEND bit is set. See “Power Management Block” on page 23. AT91SAM7A1 131 ...
Page 132
... Status Register 0xFFFC0074 Interrupt Enable Register 0xFFFC0078 Interrupt Disable Register 0xFFFC007C Interrupt Mask Register 0xFFFC0080 Convert Data Register 0xFFFC0084 – Reserved 0xFFFC008C 0xFFFC0090 Test Mode Register AT91SAM7A1 132 Name Access – – ADC_ECR Write-only ADC_DCR Write-only ADC_PMSR Read-only – – ADC_CR ...
Page 133
... AT91SAM7A1 – – – – – – – – – – ADC – – – – – – – – ...
Page 134
... ADC Power Management Status Register Name: ADC_PMSR Access: Read-only Address: 0xFFFC0058 31 30 – – – – – – – – • ADC: ADC Clock Status 0: ADC clock disabled. 1: ADC clock enabled. AT91SAM7A1 134 – – – – – – – – – – – – ...
Page 135
... STOP: Stop Conversion in Continuous Conversion 0: No effect. 1: Stop the continuous conversion. 6048B–ATARM–29-Jun- – – – – – – – – – – STOP START AT91SAM7A1 – – – – – – ADCDIS ADCEN SWRST – – 8 – 0 135 ...
Page 136
... This value indicates the number of master clock periods necessary to make 4 µs. This time is the stabilization time of the analog circuitry. For example, if CORECLK = 30 MHz, 120 periods of CORECLK are needed to obtain the absolute time of 4 µs. Thus, the STARTUPTIME value of the mode register is 120 (0x78 in hexadecimal code). AT91SAM7A1 136 – ...
Page 137
... NBRCH[2:0]: Number of Conversions NBRCH[2:0] 000 001 010 011 100 101 110 111 • CONTCV: Continuous Conversion 0: Single conversion mode. 1: Continuous conversion mode. This bit is initialized to 0. 6048B–ATARM–29-Jun-06 AT91SAM7A1 Number of Conversions 137 ...
Page 138
... Name: ADC_CMR Access: Read/Write Address: 0xFFFC0068 31 30 – CV8[2: – CV6[2: – CV4[2: – CV2[2:0] • CVx[2:0]: Input Selection the conversion number. CVx[2:0] 000 001 010 011 100 101 110 111 AT91SAM7A1 138 – – – – CV7[2: CV5[2: CV3[2: CV1[2:0] ...
Page 139
... Clear OVR interrupt. • TEND: End of PDC Transfer Interrupt 0: No effect. 1: Clear TEND interrupt. 6048B–ATARM–29-Jun- – – – – – – – – – – – TEND AT91SAM7A1 – – – – – – – – – OVR – – 139 ...
Page 140
... TEND: End of Total Transfer of PDC 0: Transfer of all data not complete. 1: PDC transfer complete. This bit is set when the transfer of all the data by the PDC is complete. When we are in continuous mode, it stops the con- version only if the STOPEN bit of the mode register is active. AT91SAM7A1 140 – ...
Page 141
... ADCENS: ADC Enable Status 0: ADC is disabled. 1: ADC is enabled. • CTCVS: Continuous Mode Status 0: Single conversion with help of microprocessor. 1: Continuous conversion, the peripheral is stand-alone. This bit is initialized to 0 and changes when there is a change of mode. This bit never generates an interrupt. 6048B–ATARM–29-Jun-06 AT91SAM7A1 141 ...
Page 142
... ADC Interrupt Disable Register Name: ADC_IDR Access: Write-only Address: 0xFFFC0078 31 30 – – – – – – – – AT91SAM7A1 142 – – – – – – – – – – – TEND – – – ...
Page 143
... OVR interrupt is enabled. • TEND: End of PDC Transfer 0: TEND interrupt is disabled. 1: TEND interrupt is enabled. 6048B–ATARM–29-Jun- – – – – – – – – – – – TEND AT91SAM7A1 – – – – – – – – – OVR READY EOC 143 ...
Page 144
... DATA[9:0]: Converted Data The resulting data from an analog to digital conversion is latched into this register at the end of a conversion and remains valid until a new conversion is completed. When this register is read, the EOC bit in the ADC_SR register is cleared. AT91SAM7A1 144 – ...
Page 145
... Normal mode 1: Test mode TEST mode must be set at to logical 1 in the SFM. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – – – – – – – – – TEST 145 ...
Page 146
... Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The AT91SAM7A1 includes three USARTs. Each transmitter and receiver module is con- nected to the Peripheral Data Controller. 18.1 Description The main features are: • Programmable baud rate generator • Parity, framing and overrun error detection • Supports Hardware LIN protocol (specification 1.2) • ...
Page 147
... SCK pin. No division is active. The value written in US_BRGR has no effect. Figure 18-2. Baud Rate Generator USCLK[0] USCLKS[1] CORECLK SCK 1 6048B–ATARM–29-Jun-06 Baud rate = Selected Clock/ Baud Rate = Selected Clock/CD CD[15:0] CD[15:0] CLK Out 16-Bit Counter > SYNC USCLKS[1] AT91SAM7A1 SYNC 0 / Baud Rate Clock 147 ...
Page 148
... When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal on each rising edge of SCK low level is detected considered as a start. Data bits, par- ity bit and stop bit are sampled and the receiver waits for the next start bit. See AT91SAM7A1 148 True Start ...
Page 149
... When the counter reaches 0, the TIMEOUT bit in US_SR is set. The user starts (or restarts) the wait for a first character by setting the STTTO (start time-out) bit in US_CR. 6048B–ATARM–29-Jun- MID PID Dum AT91SAM7A1 D6 D7 Stop Bit Parity Bit 10 Stop Bits PID Data Data ChkSum 149 ...
Page 150
... The transmitter sends an address byte (parity bit set) when a Send Address Command (SENDA) is written to US_CR. In this case, the next byte written to US_THR will be transmitted as an address. After this, any byte transmitted has the parity bit cleared. AT91SAM7A1 150 , the USART is configured to run in multidrop b Idle state duration between two characters = Time-guard Value x Bit Period 6048B– ...
Page 151
... The RXD pin level has no effect and the TXD pin is held high idle state. Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter and the Receiver are disabled and have no effect. This mode provides bit by bit retransmission. 6048B–ATARM–29-Jun-06 Clock TXD Start Bit AT91SAM7A1 Stop Bit Parity Bit 151 ...
Page 152
... RXD, SCK) of the USART to optimize the use of available package pins. These lines are controlled by the USART PIO controller. 18.8 Power Management The USART is provided with a power management block that optimizes power consumption. See ”Power Consumption” on page AT91SAM7A1 152 9. 6048B–ATARM–29-Jun-06 ...
Page 153
... Reserved 0x070 Status Register 0x074 Interrupt Enable Register 0x078 Interrupt Disable Register 0x07C Interrupt Mask Register 0x080 Receiver Holding Register 0x084 Transmitter Holding Register 6048B–ATARM–29-Jun-06 AT91SAM7A1 Name Access US_PER Write-only US_PDR Write-only US_PSR Read-only – – US_OER Write-only US_ODR ...
Page 154
... Table 18-1. USART Memory Map Offset Register 0x088 Baud Rate Generator Register 0x08C Receiver Time-out Register 0x090 Transmitter Time-guard Register AT91SAM7A1 154 Name Access US_BRGR Read/Write US_RTOR Read/Write US_TTGR Read/Write 6048B–ATARM–29-Jun-06 Reset State 0x00000000 0x00000000 0x00000000 ...
Page 155
... AT91SAM7A1 – – – RXD TXD SCK – – – – – – – – – RXD TXD SCK – ...
Page 156
... PIO is inactive on the SCK pin. 1: PIO is active on the SCK pin. • TXD: TXD Pin 0: PIO is inactive on the TXD pin. 1: PIO is active on the TXD pin. • RXD: RXD Pin 0: PIO is inactive on the RXD pin. 1: PIO is active on the RXD pin. AT91SAM7A1 156 – – – ...
Page 157
... AT91SAM7A1 – – – RXD TXD SCK – – – – – – – – – RXD TXD SCK – ...
Page 158
... PIO is an output on the SCK pin. • TXD: TXD Pin 0: PIO is an input on the TXD pin. 1: PIO is an output on the TXD pin. • RXD: RXD Pin 0: PIO is an input on the RXD pin. 1: PIO is an output on the RXD pin. AT91SAM7A1 158 – – ...
Page 159
... AT91SAM7A1 – – – RXD TXD SCK – – – – – – – – – RXD TXD SCK – ...
Page 160
... The output data for the TXD pin is programmed The output data for the TXD pin is programmed to 1. • RXD: RXD Pin 0: The output data for the RXD pin is programmed The output data for the RXD pin is programmed to 1. AT91SAM7A1 160 – ...
Page 161
... RXD: RXD Pin 0: The RXD pin is at logic 0. 1: The RXD pin is at logic 1. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – RXD TXD SCK – – – – – – 161 ...
Page 162
... USART PIO Multi Drive Disable Register Name: US_MDDR Access: Write-only Offset: 0x044 31 30 – – – – – – – – AT91SAM7A1 162 – – – – – – – – – – – – – ...
Page 163
... The RXD pin is not configured as an open drain. 1: The RXD pin is configured as an open drain. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – RXD TXD SCK – – – – – – 163 ...
Page 164
... USART Disable Clock Register Name: US_DCR Access: Write-only Offset: 0x054 31 30 – – – – – – – – AT91SAM7A1 164 – – – – – – – – – – – – – – – ...
Page 165
... USART clock disabled. 1: USART clock enabled. Note: The US_PMSR register is not reset by software reset. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – – – – – – – – USART PIO 165 ...
Page 166
... RXEN: Receiver Enable 0: No effect. 1: The receiver is enabled if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: The receiver is disabled. AT91SAM7A1 166 – – – ...
Page 167
... STTTO: Start Time-out 0: No effect. 1: Start waiting for a character before clocking the time-out counter. • SENDA: Send Address 0: No effect Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. 6048B–ATARM–29-Jun-06 AT91SAM7A1 167 ...
Page 168
... USCLKS[1:0]: Clock Selection (Baud Rate Generator Input Clock) USCLKS[1: • CHRL[1:0]: Character Length Start, stop and parity bits are added to the character length. CHRL[1: • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. AT91SAM7A1 168 – – – – – – 13 ...
Page 169
... Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved AT91SAM7A1 Parity Type Even Parity Odd Parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved 169 ...
Page 170
... No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last “Reset Status Bits” command least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last “Reset Status Bits” command. AT91SAM7A1 170 – ...
Page 171
... These bits are reset to zero following a read and at reset input change has been detected on the corresponding pin since the register was last read least one input change has been detected on the corresponding pin since the register was last read. 6048B–ATARM–29-Jun-06 AT91SAM7A1 171 ...
Page 172
... PARE FRAME USOVRE 18.9.21 USART Interrupt Disable Register Name: US_IDR Access: Write-only Offset: 0x078 31 30 – – – – – – PARE FRAME USOVRE AT91SAM7A1 172 – – – – – – – – – ENDTX ENDRX – – – ...
Page 173
... FRAME Interrupt is disabled. 1: FRAME Interrupt is enabled. • PARE: Mask Parity Error Interrupt 0: PARE Interrupt is disabled. 1: PARE Interrupt is enabled. 6048B–ATARM–29-Jun- – – – – – – USOVRE ENDTX ENDRX AT91SAM7A1 – – – – RXD TXD – IDLE TXEMPTY RXBRK ...
Page 174
... IDLE Interrupt is enabled. • SCK, TXD, RXD: PIO Interrupt M These bits show which pins have interrupts enabled. They are updated by writing to US_IER or US_IDR. 0: Interrupt is not enabled on the corresponding input pin. 1: Interrupt is enabled on the corresponding input pin. AT91SAM7A1 174 as k 6048B–ATARM–29-Jun-06 ...
Page 175
... RXCHR[7: – – – – – – – – – TXCHR[7:0] AT91SAM7A1 – – – – – – – – RXCHR[ – – – – – – – – TXCHR[ 175 ...
Page 176
... Clock divider bypassed Baud Rate (Asynchronous Mode) = Selected clock/( 65535 Baud Rate (Synchronous Mode) = Selected clock/CD Notes synchronous mode, the value programmed must be even to ensure a 50:50 mark/space ratio must not be used when internal clock (CORECLK) is selected (i.e., USCLKS[1: AT91SAM7A1 176 – – ...
Page 177
... RXEN bit in the US_CR register, the time-out restarts where it left off (i.e not reset). 6048B–ATARM–29-Jun- – – – – – – – – – TO[7:0] AT91SAM7A1 – – – – – – – – – 177 ...
Page 178
... TG[7:0]: Time-guard Value TG[7:0] Action 0 Disables the TX Time-guard function 255 TXD is inactive high after the transmission of each character for the Time-guard duration. Time-guard duration = TG x Bit period. AT91SAM7A1 178 – – – – – – – ...
Page 179
... Capture (CAPT) The AT91SAM7A1 provides a Capture module that serves as a frame analyzer. It stores the duration period (high and low level register; these durations are described as a number of counter cycles (CAPTCLK). The Capture peripheral provides data transfer with the PDC. Capture can detect all frame variations (with an error of one CAPTCLK period maximum) if the input signal has a frequency less than CAPTCLK/2 ...
Page 180
... The line is controlled by the capture PIO controller. 19.4 Power Management Each capture module (CAPT0 and CAPT1) is provided with a power management block allow- ing optimization of power consumption. AT91SAM7A1 180 Delay Max for Edge Detection 7.5 MHz 458 Hz See “ ...
Page 181
... CAP_ECR Write-only CAP_DCR Write-only CAP_PMSR Read-only – – CAP_CR Write-only CAP_MR Read/Write --- --- CAP_CSR Write-only CAP_SR Read-only CAP_IER Write-only CAP_IDR Write-only CAP_IMR Read-only CAP_DR Read-only AT91SAM7A1 Reset State --- --- 0x00010000 --- --- --- 0x00000000 --- --- --- 0x00000000 0x000X0000 --- --- 0x00000000 --- --- – – 0x00000000 – – 0x00000000 --- – 0x00000000 – ...
Page 182
... CAPTPIN: Capture Pin 0: The PIO control of the capture pin is disabled (the pin works in the capture mode). 1: The PIO control of the capture pin is enabled (the pin works as a PIO). AT91SAM7A1 182 – – – – – ...
Page 183
... AT91SAM7A1 – – – – – CAPTPIN – – – – – – – – – – – CAPTPIN – ...
Page 184
... CAPTPIN: Capture Pin 0: The PIO output is set to logical 0 on the capture pin. 1: The PIO output is set to logical 1 on the capture pin. AT91SAM7A1 184 – – – – – – – – ...
Page 185
... CAPTPIN: Capture Pin 0: The capture pin logical 0. 1: The capture pin logical 1. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 – – – – – CAPTPIN – – – – – – 185 ...
Page 186
... Offset: 0x048 31 30 – – – – – – – – • CAPTPIN: Capture Pin 0: The capture pin is not configured as an open drain. 1: The capture pin is configured as an open drain. AT91SAM7A1 186 – – – – – – – – – 5 ...
Page 187
... AT91SAM7A1 – – – – – – – – – – CAP PIO – – – – – – – ...
Page 188
... PIO: PIO Clock 0: PIO clock disabled. 1: PIO clock enabled. • CAP: CAPTURE Clock 0: Capture clock disabled. 1: Capture clock enabled. Note: The CAPT_PMSR register is not reset by a software reset. AT91SAM7A1 188 – – – – – – ...
Page 189
... If both CAPEN and CAPDIS are equal to one when the control register is written, the CAPTURE is disabled. • STARTCAPT: Start Capture 0: No effect. 1: The capture starts a new capture. 6048B–ATARM–29-Jun- – – – – – – – – – – – STARTCAPT AT91SAM7A1 – – – – – – CAPDIS CAPEN SWRST – – 8 – 0 189 ...
Page 190
... In case of an overrun, the capture does not stop writing on the Data Register. • ONESHOT: One Shot 0: The capture still captures a frame variation. 1: The module captures a frame variation and stops. To ask for another capture, the STARTCAPT bit has to be set CAPT_CR. AT91SAM7A1 190 – ...
Page 191
... CAPTPIN: Capture Pin 0: No effect. 1: Clears the CAPTPIN interrupt. 6048B–ATARM–29-Jun- – – – – – – – – – – – – AT91SAM7A1 26 25 – – – – CAPTPIN 10 9 – – OVERFLOW OVERRUN PDCEND 24 – – 0 191 ...
Page 192
... No effect. 1: Data in CAP_DR has to be read. This bit is cleared by reading the CAP_DR register. • CAPENS: Capture Enable Status 0: Capture is disabled. 1: Capture is enabled. • CAPTPIN: Capture Pin 0: No effect. 1: The capture input pin has changed state. AT91SAM7A1 192 – – – 21 ...
Page 193
... DATACAPT – – – – – – – – – – – DATACAPT AT91SAM7A1 26 25 – – – – CAPTPIN 10 9 – – OVERFLOW OVERRUN PDCEND 26 25 – – – – CAPTPIN 10 9 – – OVERFLOW ...
Page 194
... OVERRUN interrupt is enabled. • OVERFLOW: Overflow Interrupt Mask 0: OVERFLOW interrupt is disabled. 1: OVERFLOW interrupt is enabled. • DATACAPT: Data Capture Interrupt Mask 0: DATACAPT interrupt is disabled. 1: DATACAPT interrupt is enabled. • CAPTPIN: Capture Pin 0: CAPTPIN interrupt is disabled. 1: CAPTPIN interrupt is enabled. AT91SAM7A1 194 – – – – ...
Page 195
... The duration concerns a low level. 1: The duration concerns a high level. Note that if the MEASMODE[1:0] (CAPT_MR) equals 1X, the LEVEL bit is used as a duration bit. 6048B–ATARM–29-Jun- – – – – – – DURATION[14: DURATION[7:0] AT91SAM7A1 – – – – – – 195 ...
Page 196
... Simple Timer (ST) The AT91SAM7A1 microcontroller includes two 16-bit Simple Timers (ST0 and ST1) with 2 channels per simple timer. Each simple timer channel provides basic functions for timing calculation including two cas- caded dividers and a 16 bit-counter. The prescalar defines the clock frequency of the channel counter. ...
Page 197
... Each Simple Timer (ST0 and ST1) is provided with a power management block allowing opti- mization of power consumption. See 6048B–ATARM–29-Jun-06 STx_PRz SYSCAL[10:0] Programmable Divider Programmable 0 (SYSCAL) 1 LFCLK STx_PRz.4 SELECTCLK ”Power Management Block” on page AT91SAM7A1 STx_CTz LOAD[15:0] STx_PRz PRESCALAR[3:0] LOAD COUNT 16-bit Downcounter Divider (PRESCALAR) ENA CLR STx_SR CHENSz ...
Page 198
... Interrupt Disable Register 0x07C Interrupt Mask Register 0x080 Channel 0 Prescalar 0x084 Channel 0 Counter 0x088 Channel 1 Prescalar 0x08C Channel 1 Counter 0x200 Current Counter Value 0 0x204 Current Counter Value 1 AT91SAM7A1 198 Name Access – – ST_ECR Write-only ST_DCR Write-only ST_PMSR Read-only – – ST_CR Write-only – ...
Page 199
... AT91SAM7A1 – – – – – – – – – – ST – – – – – – – – ...
Page 200
... No effect. 1: Enables the Simple Timer Channel X. • CHDISX: Simple Timer Channel Disable 0: No effect. 1: Disables the Simple Timer Channel X. If both CHENX and CHDISX are equal to one when the control register is written, the Simple Timer Channel X is disabled. AT91SAM7A1 200 – ...