HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 24

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.4 Usage Notes ...................................................................................................................... 538
Section 15 A/D Converter
15.1 Overview........................................................................................................................... 541
15.2 Register Descriptions ........................................................................................................ 545
15.3 CPU Interface.................................................................................................................... 549
15.4 Operation .......................................................................................................................... 550
15.5 Interrupts ........................................................................................................................... 556
15.6 Usage Notes ...................................................................................................................... 556
Section 16 D/A Converter
16.1 Overview ............................................................................................................................ 561
16.2 Register Descriptions ........................................................................................................ 564
16.3 Operation .......................................................................................................................... 567
16.4 D/A Output Control .......................................................................................................... 568
Section 17 RAM
17.1 Overview........................................................................................................................... 569
17.2 System Control Register (SYSCR) ................................................................................... 571
17.3 Operation .......................................................................................................................... 572
Rev. 3.00 Sep 27, 2006 page xxii of xxvi
15.1.1 Features................................................................................................................ 541
15.1.2 Block Diagram ..................................................................................................... 542
15.1.3 Input Pins ............................................................................................................. 543
15.1.4 Register Configuration......................................................................................... 544
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 545
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 546
15.2.3 A/D Control Register (ADCR) ............................................................................ 548
15.4.1 Single Mode (SCAN = 0) .................................................................................... 550
15.4.2 Scan Mode (SCAN = 1)....................................................................................... 552
15.4.3 Input Sampling and A/D Conversion Time ......................................................... 554
15.4.4 External Trigger Input Timing............................................................................. 555
16.1.1 Features ................................................................................................................. 561
16.1.2 Block Diagram ..................................................................................................... 562
16.1.3 Input/Output Pins ................................................................................................. 563
16.1.4 Register Configuration......................................................................................... 563
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 564
16.2.2 D/A Control Register (DACR) ............................................................................ 564
16.2.3 D/A Standby Control Register (DASTCR).......................................................... 566
17.1.1 Block Diagram ..................................................................................................... 570
17.1.2 Register Configuration......................................................................................... 570
.................................................................................................................. 569
................................................................................................. 541
................................................................................................. 561