HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 316

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 I/O Ports
Port 8 Data Direction Register (P8DDR)
P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
Bits 7 to 5 are reserved. They cannot be modified and are always read as 1.
Bit
Modes
1 to 4
Modes
5 to 7
Modes 1 to 6 (Expanded Modes): When bits in P8DDR bit are set to 1, P8
CS
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset only CS
output. The other three pins are input ports. In modes 5 and 6 (expanded modes with on-chip
ROM enabled), following a reset all four pins are input ports.
When the refresh controller is enabled, P8
refresh controller is disabled, P8
setting. For details see table 9.15.
Mode 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an
output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 in modes 1 to 4 and H'E0 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting, so if a P8DDR bit is set to
1 while port 8 acts as an I/O port, the corresponding pin maintains its output state in software
standby mode.
Rev. 3.00 Sep 27, 2006 page 288 of 872
REJ09B0325-0300
3
output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports.
Initial value
Read/Write
Initial value
Read/Write
7
1
1
Reserved bits
0
becomes a generic input/output port according to the P8DDR
6
1
1
0
is used unconditionally for RFSH output. When the
5
1
1
P8 DDR
4
W
W
4
1
0
P8 DDR
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
3
W
W
3
0
0
P8 DDR
2
W
W
2
0
0
4
to P8
P8 DDR
1
1
W
W
1
0
0
become CS
P8 DDR
0
is
0
W
W
0
0
0
0
to