M37516F8HP Renesas Electronics America, M37516F8HP Datasheet - Page 37

• Manufacturer Part Number: M37516F8HP
• Description: IC 740 MCU FLASH 32K 48QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37516F8HP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7516 Group
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I
register (address 002D
address to the I
condition in which the ES0 bit of the I
002E
that, the bit counter becomes “000
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 34, the START condition generating timing diagram, and
Table 9, the START condition generating timing table.
Fig. 34 START condition generating timing diagram
Table 9 START condition generating timing table
Note: Absolute time at
STOP Condition Generating Method
When the ES0 bit of the I
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 35, the STOP condition generating timing
diagram, and Table 10, the STOP condition generating timing
table.
Fig. 35 STOP condition generating timing diagram
Table 10 STOP condition generating timing table
Note: Absolute time at
Rev.1.01
Setup time
Setup time
I
w r i t e s i g n a l
S
S
Hold time
Hold time
I
w r i t e s i g n a l
S
S
2
2
C s t a t u s r e g i s t e r
C L
DA
C L
D A
C s t a t u s r e g i s t e r
Item
Item
16
number of
number of
2
) and the BB flag are “0”, a START condition occurs. After
C status register (address 002D
Jul 01, 2003
2
Standard clock mode
Standard clock mode
cycles.
cycles.
C data shift register (address 002B
5.0 s (20 cycles)
5.0 s (20 cycles)
5.0 s (20 cycles)
4.5 s (18 cycles)
= 4 MHz. The value in parentheses denotes the
= 4 MHz. The value in parentheses denotes the
16
) at the same time after writing the slave
2
C control register (address 002E
Setup
S e t u p
time
t i m e
page 35 of 89
2
” and an S
Hold time
H o l d t i m e
2
C control register (address
16
High-speed clock mode
High-speed clock mode
2.5 s (10 cycles)
2.5 s (10 cycles)
) simultaneously. Then a
3.0 s (12 cycles)
2.5 s (10 cycles)
CL
for 1 byte is out-
16
) with the
2
C status
16
) is
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 36, 37, and Table 11. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the S
lease time, setup time, and hold time (see Table 11).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 11, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
Fig. 36 START condition detecting timing diagram
Fig. 37 STOP condition detecting timing diagram
Table 11 START condition/STOP condition detecting conditions
Note: Unit : Cycle number of system clock
BB flag set/
reset time
Setup time
S
Hold time
CL
release time
interrupt request signal “IICIRQ” occurs to the CPU.
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I
STOP condition control register is set to “18
S
S
BB flag
S
S
BB flag
CL
DA
CL
DA
CL
SSC value –1
SSC value + 1
SSC value + 1
SSC value + 1 cycle (6.25 s)
and S
Standard clock mode
2
2
2
Setup
S e t u p
time
S
DA
S
t i m e
CL
C L
pins satisfy three conditions: S
cycle < 4.0 s (3.125 s)
cycle < 4.0 s (3.125 s)
release time
+ 2 cycles (3.375 s)
r e l e a s e t i m e
H o l d t i m e
H o l d t i m e
B B f l a g
r e s e t
t i m e
B B f l a g
r e s e t
t i m e
16
” at
High-speed clock mode
4 cycles (1.0 s)
2 cycles (1.0 s)
2 cycles (0.5 s)
3.5 cycles (0.875 s)
= 4 MHz.
2
C START/
CL
re-