M37516F8HP Renesas Electronics America, M37516F8HP Datasheet - Page 38

• Manufacturer Part Number: M37516F8HP
• Description: IC 740 MCU FLASH 32K 48QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37516F8HP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7516 Group
[I
(S2D)] 0030
The I
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(X
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 11.
Do not set “00000
tion set bit (SSC4 to SSC0).
Refer to Table 12, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the S
Rev.1.01
2
C START/STOP Condition Control Register
2
lection bit, the S
interface enable bit ES0, the S
set. When selecting the S
rupt before the S
S
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
C START/STOP condition control register (address 0030
DA
interrupt pin selection bit, or the I
Jul 01, 2003
16
2
” or an odd number to the START/STOP condi-
CL
CL
/S
/S
DA
DA
interrupt pin selection bit, or the I
interrupt pin polarity selection bit, the S
IN
CL
page 36 of 89
) because these time are measured
/S
DA
CL
interrupt source, disable the inter-
/S
CL
DA
/S
2
interrupt request bit may be
C-BUS interface enable bit
DA
interrupt pin polarity se-
2
C-BUS
16
CL
)
/
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I
(address 002C
parison of the RWB bit of the I
002C
when the 7-bit addressing format is selected, refer to Figure 39,
(1) and (2).
7-bit addressing format
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I
comparison, an address comparison between the RWB bit of
the I
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I
“1.” After the second-byte address data is stored into the I
data shift register (address 002B
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RWB bit of the I
(address 002C
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I
mission format when the 10-bit addressing format is selected,
refer to Figure 39, (3) and (4).
2
2
C control register (address 002E
16
2
2
C address register (address 002C
C control register (address 002E
C address register (address 002C
2
) is not performed. For the data transmission format
C address register (address 002C
16
16
). At the time of this comparison, address com-
) to “1” by software. This processing can make
2
C status register (address 002D
2
C address register (address
16
), perform an address com-
16
16
16
) to “0.” The first 7-bit
16
). For the data trans-
) to “1.” An address
16
2
2
). At the time of this
C address register
C address register
) and the R/W bit
16
) is set to
2
C