M37516F8HP Renesas Electronics America, M37516F8HP Datasheet - Page 44

• Manufacturer Part Number: M37516F8HP
• Description: IC 740 MCU FLASH 32K 48QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37516F8HP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7516 Group
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
0035
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion
[AD Control Register (ADCON)] 0034
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
Channel Selector
The channel selector selects one of ports P3
inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
When the A-D converter is operated at low-speed mode, f(X
and f(X
the A-D converter has a built-in self-oscillation circuit.
Fig. 46 Block diagram of A-D converter
Rev.1.01
SS
and V
16
CIN
, 0036
) do not have the lower limit of frequency, because of
REF
IN
Jul 01, 2003
) to 500 kHz or more during an A-D conversion.
into 1024 and outputs the divided voltages.
16
AD control register
P3
P3
P3
P3
P3
P3
P3
P3
(Address 0034
0
3
4
6
7
1
2
5
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
page 42 of 89
0
1
2
3
4
5
6
7
16
)
0
/AN
0
Comparator
to P3
b7
3
16
7
/AN
7
A-D control circuit
and
Data bus
IN
)
A-D conversion high-order register
A-D conversion low-order register
Resistor ladder
V
Fig. 44 Structure of AD control register
Fig. 45 Structure of A-D conversion registers
REF
AV
b7
10
Note : The high-order 6 bits of address 0036
10-bit reading
(Read address 0036
(Address 0036
(Address 0035
8-bit reading (Read only address 0035
(Address 0035
SS
b0
at reading.
16
16
16
)
)
)
A-D interrupt request
b0
16
AD control register
(ADCON : address 0034
(Address 0036
(Address 0035
b7
b7
b7
Analog input pin selection bits
0 0 0: P3
0 0 1: P3
0 1 0: P3
0 1 1: P3
1 0 0: P3
1 0 1: P3
1 1 0: P3
1 1 1: P3
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7 b6 b5 b4 b3 b2 b1 b0
b9 b8 b7 b6 b5 b4 b3 b2
b2 b1 b0
before 0035
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
16
16
16
16
become “0”
)
)
)
16
b9
16
)
)
b0
b8
b0
b0