AK5384VFP AKM Semiconductor Inc, AK5384VFP Datasheet - Page 12

• Manufacturer Part Number: AK5384VFP
• Description: IC ADC AUDIO STER 24BIT 28VSOP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5384VFP

• Resolution (bits): 24 b
• Sampling Rate (per Second): 8k ~ 96k
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LSSOP (0.220", 5.60mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Interface: -
• Other names: 974-1031-2; AK5384VFP

n System Clock
The external clocks which are required to operate the AK5384 are MCLK(256fs/384fs/512fs/768fs), BICK(48fs ),
LRCK(1fs) in slave mode (M/S pin = “L”). MCLK should be synchronized with LRCK but the phase is not critical. When
384fs, 512fs or 768fs clock is input to MCLK pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x
1/2=768fs x 1/3) automatically. Table 1 illustrates standard audio word rates and corresponding frequencies used in the
AK5384.
In master mode (M/S pin = “H”), MCLK select 256fs or 512fs by CKS pin. But 384fs and 768fs are not supported. 512fs
does not support 96kHz sampling.
All external clocks (MCLK, BICK, LRCK) should always be present whenever the AK5384 is in normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK5384 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the
AK5384 should be in the power-down mode (PDN pin = “L”). After exiting reset at power-up etc., the AK5384 is in the
power-down mode until MCLK and LRCK are input. In master mode, the master clock (MCLK) must be provided unless
PDN pin = “L”.
n Audio Interface Format
12 types of audio data interface can be selected by the TDM1-0, M/S and DIF pins as shown in Table 3. The audio data
format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The SDTO1/2 is
clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock in
Mode 2-3.
In TDM256 mode, the serial data of all ADC (four channels) is output from the SDTO1/2 pins. BICK should be fixed to
256fs. In the slave mode, “H” time and “L” time of LRCK should be 1/256fs at least. In the master mode, “H” time (“L”
time at I
In TDM128 mode, the serial data of all ADC (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed to
“L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be 1/128fs at least. In the
master mode, “H” time (“L” time at I
MS0225-E-00
32.0kHz
44.1kHz
48.0kHz
96.0kHz
2
S mode) of LRCK is 1/8fs typically. TDM256 mode does not support 96kHz sampling.
fs
11.2896MHz
12.2880MHz
24.5760MHz
8.1920MHz
256fs
CKS
Table 2. Master clock frequency select (Master mode)
H
L
12.2880MHz
16.9344MHz
18.4320MHz
36.8640MHz
2
S mode) of LRCK is 1/4fs typically. TDM128 mode supports up to 96kHz sampling.
Table 1. System clock example (Slave mode)
384fs
OPERATION OVERVIEW
8kHz
MCLK
16.3840MHz
22.5792MHz
24.5760MHz
256fs
512fs
fs
512fs
N/A
- 12 -
48kHz
MCLK
33.8688MHz
36.8640MHz
24.576MHz
48kHz
768fs
N/A
256fs
N/A
fs
96kHz
2.0480MHz
2.8224MHz
3.0720MHz
6.1440MHz
64fs
BICK
4.0960MHz
5.6448MHz
6.1440MHz
128fs
N/A
2003/05