AK5384VFP AKM Semiconductor Inc, AK5384VFP Datasheet - Page 15

• Manufacturer Part Number: AK5384VFP
• Description: IC ADC AUDIO STER 24BIT 28VSOP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5384VFP

• Resolution (bits): 24 b
• Sampling Rate (per Second): 8k ~ 96k
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LSSOP (0.220", 5.60mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Interface: -
• Other names: 974-1031-2; AK5384VFP

ASAHI KASEI
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz(@fs=48kHz)
and scales with sampling rate (fs).
n Overflow Detection
The AK5384 has overflow detect function for analog input. OVF pin goes to “H” if one of 4-channels overflows (more
than 0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC
(GD=27.6/fs=575µs@fs=48kHz). OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after PDN pin = “ ”, and then overflow
detection is enabled.
n Power down
The AK5384 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM are AVSS level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO1/2 becomes available after
516 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2’s
complement “0”. The ADC outputs settle in the data corresponding to the input signals after the end of initialization
(Settling approximately takes the group delay time).
Notes:
n System Reset
The AK5384 should be reset once by bringing PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at I
MS0225-E-00
Internal
A/D In
A/D Out
Clock In
MCLK,LRCK,BICK
PDN
(Analog)
(Digital)
(1) Digital output corresponding to analog input has the group delay (GD).
(2) ADC output is “0” data at the power-down state.
(3) When the external clocks (MCLK, BICK, LRCK) are stopped, the AK5384 should be in the power-down state.
State
Normal Operation
2
S mode) of LRCK upon exiting from reset.
Idle Noise
GD
Figure 7. Power-down/up sequence example
(1)
(3)
Power-down
“0”data
(2)
- 15 -
516/fs(10.75ms@fs=48kHz)
Initialize
“0”data
Idle Noise
Normal Operation
GD
[AK5384]
2003/05