DSP56321VL275 Freescale Semiconductor, DSP56321VL275 Datasheet - Page 36

• Manufacturer Part Number: DSP56321VL275
• Description: IC DSP 24BIT 275MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56321VL275

• Interface: Host Interface, SSI, SCI
• Clock Rate: 275MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 576kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.60V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
2-16
Notes:
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. V
11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers
12. After the external host writes a new value to the ICR, the HI08 will be ready for operation after three DSP clock cycles (3 × Tc).
H[0–7]
HREQ
HACK
See the Programmer’s Model section in the chapter on the HI08 in the DSP56321 Reference Manual .
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the
Single Data Strobe mode.
The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.
The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the
Little Endian mode (HLEND = 1).
In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.
CCQH
Characteristic
= 3.3 V ± 0.3 V, V
Figure 2-13.
Table 2-10.
10
CCQL
Host Interrupt Vector Register (IVR) Read Timing Diagram
= 1.6 V ± 0.1 V; T
DSP56321 Technical Data, Rev. 11
Host Interface Timings
Expression
326
327
J
= –40°C to +100 °C, C
317
Min
200 MHz
Max
1,2,12
L
Min
329
= 50 pF
220 MHz
(Continued)
Max
328
Min
240 MHz
318
Max
Freescale Semiconductor
Min
275 MHz
Max
Uni
t