XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet - Page 22

• Manufacturer Part Number: XR16L788IQ-F
• Description: IC UART 64B 3.3V OCTAL 100QFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L788IQ-F

• Number Of Channels: 8
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1284

XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
The XR16L788 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. The four registers are in the device configuration register address space.
All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details of the source of each channel’s interrupt with its unique 3-
bit encoding.
wake-up interrupts are masked in the device configuration registers,
generated by the 788 when awakened from sleep if all 8 channels were placed in the sleep mode previously.
Reading INT0 will clear this wake-up interrupt.
Each bit gives an indication of the channel that has requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate register of the interrupting UART channel register (ISR, LSR
and MSR).
INT3, INT2 and INT1 provide a 24-bit (3 bits per channel) encoded interrupt indicator.
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt.
For other channels, interrupt 7 is reserved.
.
F
3.1.1
3.1.1.1
3.1.1.2
IGURE
Bit
2
Channel-7
14. T
Bit
1
The Global Interrupt Source Registers
See Table 13
Bit
0
HE
INT0 Channel Interrupt Indicator:
INT1, INT2 and INT3 Interrupt Source Locator
Figure 14
INT3 Register
Bit
G
2
Channel-6
LOBAL
Bit
1
Bit
0
shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep
I
for interrupt clearing details.
NTERRUPT
Bit
2
Channel-5
Ch-7
Bit-7
[0x00]
Bit
INT3
1
R
Bit
Ch-6
Bit-6
0
Individual UART Channel Interrupt Status
EGISTERS
Bit
2
Channel-4
Ch-5
Bit-5
INT0, INT1, INT2 and INT3
Bit
1
[0x00]
INT2
Interrupt Registers,
, INT0, INT1, INT2
INT2 Register
INT0 Register
Bit
Ch-4
Bit-4
0
Bit
22
2
Channel-3
Ch-3
Bit-3
Bit
1
[0x00]
INT1
Bit-2
Ch-2
Bit
0
Bit
2
AND
Ch-1
Channel-2
Bit-1
Ch-7
Bit-7
Bit
1
INT3
TIMERCNTL and SLEEP.
[0x00]
INT0
Ch-6
Bit-6
Ch-0
Bit-0
Bit
0
Ch-5 Ch-4
Bit-5
Bit
2
Channel-1
INT0 Register
Bit-4
INT1 Register
Bit
1
Ch-3 Ch-2
Bit-3
Table 9
Bit
0
Bit-2
Bit
2
Channel-0
Ch-1 Ch-0
Bit-1
shows the 3 bit
Bit
1
An interrupt is
Bit-0
Bit
0
REV. 1.2.3