XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet - Page 41

• Manufacturer Part Number: XR16L788IQ-F
• Description: IC UART 64B 3.3V OCTAL 100QFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L788IQ-F

• Number Of Channels: 8
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1284

REV. 1.2.3
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
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•
EFR[5]: Special Character Detect Enable
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•
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/
DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level
and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will re-
assert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-
7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection
for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when
hardware flow control is disabled.
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•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
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•
Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take
advantage of the FIFO level byte counter for faster data loading to the transmit FIFO., which reduces CPU
bandwidth requirements.
An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO
trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger
level.
4.14
4.15
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt.
Logic 0 = Automatic RTS/DTR flow control is disabled (default).
Logic 1 = Enable Automatic RTS/DTR flow control.
Logic 0 = Automatic CTS/DSR flow control is disabled (default).
Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts
(HIGH). Transmission resumes when CTS/DSR# pin is asserted (LOW). The selection for CTS# or DSR# is
through MCR bit-2.
TXCNT[7:0]: Transmit FIFO Level Counter - Read Only
TXTRG [7:0]: Transmit FIFO Trigger Level - Write Only
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HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
XR16L788