MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 13

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
Table 11.
MFRC500_33
Product data sheet
PUBLIC
EEPROM
byte
address
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Register
address
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Shipment content of StartUp configuration file
9.2.2.3 Register initialization file (read/write)
9.2.3.1 Key format
9.2.3 Crypto1 keys (write only)
Value
08h
07h
06h
0Ah
02h
00h
00h
The EEPROM memory content from block address 3 to 7 can initialize register
subaddresses 10h to 2Fh when the LoadConfig command is executed (see
Section 11.4.1 on page
as a two byte argument for the initialization procedure.
The byte assignment is shown in
Table 12.
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data.
Remark: The register initialization file can be read/written by users and these bytes can
be used to store other user data.
After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A
protocol.
MIFARE security requires specific cryptographic keys to encrypt data stream
communication on the contactless interface. These keys are called Crypto1 keys.
Keys stored in the EEPROM are written in a specific format. Each key byte must be split
into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This
format is a precondition for successful execution of the LoadKeyE2 (see
page
EEPROM byte address
EEPROM starting byte address
EEPROM + 1 starting byte address
EEPROM + 31 starting byte address
81) and LoadKey commands (see
Symbol
FIFOLevel
TimerClock
TimerControl
TimerReload
IRQPinConfig
PreSet2E
PreSet2F
Byte assignment for register initialization at startup
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 15 March 2010
79). This command requires the EEPROM starting byte address
Description
configuration
TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
Timer is started at the end of transmission, stopped at the beginning
of reception
TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
pin IRQ is set to high-impedance
-
-
WaterLevel[5:0] FIFO buffer warning level is set to standard
048033
…continued
Table
12.
Section 11.6.2 on page
Highly Integrated ISO/IEC 14443 A Reader IC
Register address
10h
11h
…
2Fh
81).
MFRC500
© NXP B.V. 2010. All rights reserved.
Section 11.6.1 on
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