MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 15

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
9.3.2 Controlling the FIFO buffer
9.3.3 FIFO buffer status information
When the microprocessor starts a command, the MFRC500 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses.
during command processing.
Table 13.
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
The microprocessor can get the following FIFO buffer status data:
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The MFRC500 can generate an interrupt signal when:
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by
Active
command
StartUp
Idle
Transmit
Receive
Transceive
WriteE2
ReadE2
LoadKeyE2
LoadKey
Authent1
Authent2
LoadConfig
CalcCRC
•
•
•
•
•
•
the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
the FIFO buffer full warning: bit HiAlert
the FIFO buffer empty warning: bit LoAlert
the FIFO buffer overflow warning: bit FIFOOvfl.
bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
FIFO buffer access
All information provided in this document is subject to legal disclaimers.
FIFO buffer
μp Write
-
-
yes
-
yes
yes
yes
yes
yes
yes
-
yes
yes
Rev. 3.3 — 15 March 2010
μp Read
-
-
-
yes
yes
-
yes
-
-
-
-
-
-
048033
Table 13
Highly Integrated ISO/IEC 14443 A Reader IC
Remark
the microprocessor has to know the state of the
command (transmitting or receiving)
the microprocessor has to prepare the arguments,
afterwards only reading is allowed
gives an overview of FIFO buffer access
Equation
1:
MFRC500
© NXP B.V. 2010. All rights reserved.
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