PIC18F26K22-I/SO Microchip Technology, PIC18F26K22-I/SO Datasheet - Page 156

• Manufacturer Part Number: PIC18F26K22-I/SO
• Description: IC PIC MCU 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K22-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1KB
• Ram Memory Size: 3896Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Processor Series: PIC18F
• Core: PIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
REGISTER 10-10: LATx: PORTx OUTPUT LATCH REGISTER
REGISTER 10-11: LATE: PORTE OUTPUT LATCH REGISTER
REGISTER 10-12: WPUB: WEAK PULL-UP PORTB REGISTER
DS41412A-page 156
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1: Available on PIC18(L)F4XK22 devices only.
R/W-x/u
WPUB7
LATx7
R/W-1
U-0
—
2:
2: Writes to PORTA are written to corresponding LATA register. Reads from PORTA register is return of I/O
Register Description for LATA, LATB, LATC and LATD.
Writes to PORTA are written to corresponding LATA register. Reads from PORTA register is return of I/O
pin values.
pin values.
LATx<7:0>: PORTx Output Latch bit value
Unimplemented: Read as ‘0’
LATE<2:0>: PORTE Output Latch bit value
WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled on PORT pin
1 = Pull-up disabled on PORT pin
R/W-x/u
WPUB6
LATx6
R/W-1
U-0
—
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-x/u
WPUB5
LATx5
R/W-1
U-0
—
R/W-x/u
WPUB4
LATx4
R/W-1
U-0
Preliminary
—
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x/u
WPUB3
LATx3
R/W-1
U-0
—
(1)
(1)
R/W-x/u
R/W-x/u
WPUB2
LATE2
LATx2
R/W-1
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
R/W-x/u
R/W-x/u
WPUB1
LATE1
LATx1
R/W-1
R/W-x/u
R/W-x/u
WPUB0
LATE0
LATx0
R/W-1
bit 0
bit 0
bit 0