DS92LV0411SQE/NOPB National Semiconductor, DS92LV0411SQE/NOPB Datasheet
DS92LV0411SQE/NOPB
Specifications of DS92LV0411SQE/NOPB
Related parts for DS92LV0411SQE/NOPB
DS92LV0411SQE/NOPB Summary of contents
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... DS92LV2411 or DS92LV2412. This al- lows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVC- MOS. Applications Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS92LV0411 / DS92LV0412 Features ■ ...
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Block Diagrams Ordering Information NSID Package Description DS92LV0411SQE 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS92LV0411SQ 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS92LV0411SQX 36–pin LLP, 6.0 X 6.0 X 0.8 mm, ...
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DS92LV0411 Pin Diagram DS92LV0411 Pin Descriptions Pin Name Pin # I/O, Type Channel Link Parallel Input Interface RxIN[3:0]+ 2, 33, 31 LVDS RxIN[3:0]- 1, 34, 32, 30, I, LVDS 28 RxCLKIN LVDS RxCLKIN LVDS ...
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Pin Name Pin # I/O, Type VODSEL 20 I, LVCMOS w/ pull-down De-Emph 19 I, Analog w/ pull-up MAPSEL 26 I, LVCMOS w/ pull-down CONFIG 10 LVCMOS [1:0] w/ pull-down ID[ Analog SCL 6 I, LVCMOS ...
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DS92LV0412 Pin Diagram DS92LV0412 Pin Descriptions Pin Name Pin # I/O, Type Channel Link II Serial Interface RIN CML RIN CML CMF 42 I, Analog Channel Link Parallel Output Interface RxIN[3:0]+ 15, 19, 21 ...
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Pin Name Pin # I/O, Type LVCMOS Outputs LOCK 27 O, LVCMOS LOCK Status Output Control and Configuration PDB 1 I, LVCMOS w/ pull-down VODSEL 33 I, LVCMOS w/ pull-down OEN 30 I, LVCMOS w/ pull-down OSS_SEL 35 I, LVCMOS ...
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Pin Name Pin # I/O, Type Optional Serial Bus Control ID[ Analog SCL 5 I, LVCMOS Open Drain SDA 4 I/O, LVCMOS Open Drain Power and Ground (see NOTE below) VDDL 6, 31 Power VDDA 38, 43 Power ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO Supply Voltage – V DDTX (1.8V, Ser)) Supply Voltage – V DDTX (3.3V, Des) ...
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Symbol Parameter DS92LV0412 LVCMOS I/O DC SPECIFICATIONS V High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN V High Level Output Voltage OH V Low Level Output Voltage OL I Output Short Circuit Current ...
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Symbol Parameter DS92LV0411 Channel Link II CML DRIVER DC SPECIFICATIONS V Differential Output Voltage OD Differential Output Voltage V ODp-p (DOUT+) – (DOUT-) ΔV Output Voltage Unbalance OD Offset Voltage – Single-ended & B, Figure ...
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Symbol Parameter I Supply Current Power Down DDZ I DDTXZ I DDIOZ Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter DS92LV0411 CHANNEL LINK PARALLEL LVDS INPUT t Receiver Strobe Position-bit 0 RSP0 t Receiver ...
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Symbol Parameter DS92LV0411 Channel Link II CML OUTPUT t Output Low-to-High Transition HLT Time Figure 3 t Output High-to-Low Transition HLT Time Figure 4 t Ouput Active to OFF Delay, XZD Figure 9 t PLL Lock Time, Figure 7 PLD ...
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Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter f SCL Clock Frequency SCL t SCL Low Period LOW t SCL High Period HIGH t Hold time for a start ...
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Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Note 5: When the device ...
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FIGURE 4. DS92LV0411 Output Transition Times FIGURE 5. DS92LV0411 LVDS Receiver Strobe Positions 15 30125247 30125261 www.national.com ...
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FIGURE 6. DS92LV0412 LVDS Transmitter Pulse Positions www.national.com FIGURE 7. DS92LV0411 Lock Time FIGURE 8. DS92LV0412 Lock Time 16 30125270 30125248 30125268 ...
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FIGURE 9. DS92LV0411 Disable Time FIGURE 10. DS92LV0411 Latency Delay FIGURE 11. DS92LV0412 Latency Delay 17 30125249 30125210 30125267 www.national.com ...
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FIGURE 12. DS92LV0411 Output Jitter FIGURE 13. DS92LV0412 Output State Diagram 18 30125250 30125275 ...
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FIGURE 14. DS92LV0412 Power Down Delay FIGURE 15. DS92LV0412 Enable Delay FIGURE 16. Checkerboard Data Pattern 19 30125279 30125280 30125232 www.national.com ...
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FIGURE 17. BIST PASS Waveform FIGURE 18. Serial Control Bus Timing Diagram 20 30125252 30125236 ...
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Functional Description The DS92LV0411 / DS92LV0412 chipset transmits and re- ceives 24-bits of data and 3 control signals, formatted as Channel Link LVDS data, over a single serial CML pair oper- ating at 140 Mbps to 1.4 Gbps serial line ...
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FIGURE 20. 8–bit Channel Link Mapping: LSB's on RxIN3 FIGURE 21. 8–bit Channel Link Mapping: MSB's on RxIN3 www.national.com 22 30125265 30125266 ...
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VIDEO CONTROL SIGNAL FILTER The three control bits can be used to communicate any low speed signal. The most common use for these bits is in the display or machine vision applications display application these bits are typically ...
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TABLE 4. De-Emphasis Resistor Value De-Emphasis Setting Resistor Value (kΩ) Open Disabled FIGURE 23. De-Emph vs. R value POWER SAVING FEATURES Ser — Power ...
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INPUTS OUTPUTS PDB OEN OSS_SEL LOCK DES — INTEGRATED SIGNAL CONDITIONING FEATURES — DES Des — ...
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EMI REDUCTION FEATURES Des — VOD Select (VODSEL) The differential output voltage of the Channel Link interface is controlled by the VODSEL input. TABLE 7. Des — Differential Output Voltage Table VODSEL Result L VOD is 250 mV TYP (500 ...
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TABLE 9. SSCG Configuration (LF_MODE = H) — Des Output SSC[2:0] Inputs LF_MODE = H (5 — 20 MHz) SSC2 Power Saving Features Des — Power Down Feature (PDB) The DS92LV0412 has ...
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Built In Self Test (BIST) An optional At-Speed Built In Self Test (BIST) feature sup- ports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In ...
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Optional Serial Bus Control The DS92LV0411 and DS92LV0412 may be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configu- ration is set by ...
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To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred acknowl- edge bit (ACK slave on the bus is ...
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TABLE 12. DS92LV0411 SERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Ser Config 3 Device De-Emphasis 7:5 Control 4 ...
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TABLE 13. DS92LV0412 DESERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Des Config 1 3 Device ID 6 Des Features 1 5:4 2:0 www.national.com R/W Defa Function ult (bin) ...
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ADD ADD Register Name Bit(s) (dec) (hex Des Features 2 7 2:0 R/W Defa Function Description ult (bin) R/W 000 EQ Gain 000: ~1.625 dB 001: ~3.25 dB 010: ~4.87 dB 011: ~6.5 dB 100: ~8.125 ...
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Applications Information DISPLAY APPLICATION The DS92LV0411 and DS92LV0412 chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats RGB888 application, ...
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DS92LV0412 TYPICAL APPLICATION CONNECTION shows a typical application of the DS92LV0412 for a 50 MHz 24-bit Color Display Application. The CML inputs require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are ...
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POWER UP REQUIREMENTS AND PDB PIN The VDD (V and V ) supply ramp should be faster than DDn DDIO 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed ...
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TABLE 14. Serializer Alternate Color / Data Mapping Channel Link Bit Number RGB (LSB Example) RxIN3 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 RxIN2 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit ...
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TABLE 15. Deserializer Alternate Color / Data Mapping Channel Link Bit Number TxOUT3 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 TxOUT2 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 ...
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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to ...
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Physical Dimensions inches (millimeters) unless otherwise noted 36–pin LLP Package (6 6 0.8 mm, 0.5 mm pitch) DS92LV0412 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) NS Package Number SQA48A ...
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