DS92LV0411SQE/NOPB National Semiconductor, DS92LV0411SQE/NOPB Datasheet - Page 34

• Manufacturer Part Number: DS92LV0411SQE/NOPB
• Description: IC SER/DESER 5-50MHZ 24B 36-LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV0411SQE/NOPB

• Serdes Function: Serializer
• Data Rate: 1.2Gbps
• Ic Output Type: CML
• No. Of Inputs: 4
• No. Of Outputs: 2
• Supply Voltage Range: 1.71V To 1.89V, 3V To 3.6V
• Driver Case Style: LLP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV0411SQE/NOPBTR

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Applications Information
DISPLAY APPLICATION
The DS92LV0411 and DS92LV0412 chipset is intended for
interface between a host (graphics processor) and a Display.
It supports an 24-bit color depth (RGB888) and up to 1024 X
768 display formats. In a RGB888 application, 24 color bits
(R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control
bits (VS, HS and DE) are supported across the serial link with
PCLK rates from 5 to 50 MHz. The chipset may also be used
in 18-bit color applications. In this application three to six gen-
eral purpose signals may also be sent from host to display.
DS92LV0411 TYPICAL APPLICATION CONNECTION
Figure 31
a 50 MHz 24-bit Color Display Application. The LVDS inputs
require external 100 ohm differential termination resistors.
The CML outputs require 0.1 μF AC coupling capacitors to the
shows a typical application of the DS92LV0411 for
FIGURE 31. DS92LV0411 Typical Connection Diagram
34
line. The line driver includes internal termination. Bypass ca-
pacitors are placed near the power supply pins. At a minimum,
four 0.1 µF capacitors and a 4.7 µF capacitor should be used
for local device bypassing. System GPO (General Purpose
Output) signals control the PDB and BISTEN pins. The ap-
plication assumes the companion deserializer (DS92LV0412)
therefore the configuration pins are also both tied Low. In this
example the cable is long, therefore the VODSEL pin is tied
High and a De-Emphasis value is selected by the resistor R1.
The interface to the host is with 1.8 V LVCMOS levels, thus
the VDDIO pin is connected also to the 1.8V rail. The Optional
Serial Bus Control is not used in this example, thus the SCL,
SDA and ID[x] pins are left open. A delay cap is placed on the
PDB signal to delay the enabling of the device until power is
stable. Bypass capacitors are placed near the power supply
pins. Ferrite beads are placed on the power lines for effective
noise suppression.
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