DS92LV0411SQE/NOPB National Semiconductor, DS92LV0411SQE/NOPB Datasheet - Page 6

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DS92LV0411SQE/NOPB

Manufacturer Part Number
DS92LV0411SQE/NOPB
Description
IC SER/DESER 5-50MHZ 24B 36-LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV0411SQE/NOPB

Serdes Function
Serializer
Data Rate
1.2Gbps
Ic Output Type
CML
No. Of Inputs
4
No. Of Outputs
2
Supply Voltage Range
1.71V To 1.89V, 3V To 3.6V
Driver Case Style
LLP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS92LV0411SQE/NOPBTR
www.national.com
Pin Name
LVCMOS Outputs
LOCK
Control and Configuration
PDB
VODSEL
OEN
OSS_SEL
LFMODE
MAPSEL
CONFIG
[1:0]
SSC[2:0]
RES
Control and Configuration — STRAP PIN
EQ
Optional BIST Mode
BISTEN
PASS
28 [PASS]
11, 10
7, 2, 3
Pin #
27
33
30
35
36
34
37
29
28
1
O, LVCMOS PASS Output (BIST Mode) — Optional
O, LVCMOS LOCK Status Output
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I/O, Type
STRAP
Description
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
See Table
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
PDB = 0, Device is powered down and the outputs are TRI-STATE®
Control Registers are RESET.
Parallel LVDS Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
Output Enable.
See
Output Sleep State Select Input.
See
SSCG Low Frequency Mode — Pin or Register Control
LF_MODE = 1, low frequency mode (TxCLKOUT = 10–20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20–65 MHz)
SSCG not avaialble above 65 MHz.
Channel Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on TxOUT3+/-.
MAPSEL = 0, LSB on TxOUT3+/-.
Operating Modes
Determine the device operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG [1:0] = 11: Interfacing to DS90C241
Spread Spectrum Clock Generation (SSCG) Range Select
See
Reserved
EQ Gain Control of Channel Link II Serial Input
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~ 1.625 dB)
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
PASS =1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Table
Table
Table
Table
5.
5.
8,
Table 9
5.
6

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