DS92LV0411SQE/NOPB National Semiconductor, DS92LV0411SQE/NOPB Datasheet - Page 23

• Manufacturer Part Number: DS92LV0411SQE/NOPB
• Description: IC SER/DESER 5-50MHZ 24B 36-LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV0411SQE/NOPB

• Serdes Function: Serializer
• Data Rate: 1.2Gbps
• Ic Output Type: CML
• No. Of Inputs: 4
• No. Of Outputs: 2
• Supply Voltage Range: 1.71V To 1.89V, 3V To 3.6V
• Driver Case Style: LLP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV0411SQE/NOPBTR

VIDEO CONTROL SIGNAL FILTER
The three control bits can be used to communicate any low
speed signal. The most common use for these bits is in the
display or machine vision applications. In a display application
these bits are typically assigned as: Bit 26 – DE, Bit 24 – HS,
Bit 25 – VS. In the machine vision standard, Camera Link,
these bits are typically assigned: Bit 26 – DVAL, Bit 24 –
LVAL, Bit 25 – FVAL.
When operating the devices in Normal Mode, the Video Con-
trol Signals (DE, HS, VS) have the following restrictions:
•
•
•
Video Control Signals are defined as low frequency signals
with limited transitions. Glitches of a control signal can cause
a visual display error. This feature allows for the chipset to
validate and filter out any high frequency noise on the control
signals. See
SERIALIZER FUNCTIONAL DESCRIPTION
The Ser converts a Channel Link LVDS clock and data bus
(4 LVDS data channels + 1 LVDS clock) to a single serial
output data stream, and also acts as a signal generator for
the chipset Built In Self Test (BIST) mode. The device can be
configured via external pins or through the optional serial
control bus. The Ser features enhanced signal quality on the
link by supporting: a selectable VOD level, a selectable de-
emphasis signal conditioning and also the Channel Link II
data coding that provides randomization, scrambling, and DC
Balanacing of the data. The Ser includes multiple features to
reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the serial data
and also the system spread spectrum clock support. The Ser
features power saving features with a sleep mode, auto stop
clock feature, and optional 1.8 V or 3.3V I/O compatibility.
See also the Functional Description of the chipset's serial
control bus and BIST modes.
Normal Mode with Control Signal Filter Enabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
Normal Mode with Control Signal Filter Disabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
VS — Only 1 transition per 130 clock cycles are
transmitted, minimum pulse width is 130 clock cycles.
FIGURE 22. Video Control Signal Filter Wavefrom
Figure
22.
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23
EMI REDUCTION FEATURES
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process
which enables the use of AC coupled interconnects and also
helps to manage EMI. The serializer first passes the parallel
data through a scrambler which randomizes the data. The
randomized data is then DC balanced. The DC balanced and
randomized data then goes through a bit shuffling circuit and
is transmitted out on the serial line. This encoding process
helps to prevent static data patterns on the serial stream. The
resulting frequency content of the serial stream ranges from
the parallel clock frequency to the nyquist rate. For example,
if the Ser / Des chip set is operating at a parallel clock fre-
quency of 50 MHz, the resulting frequency content of serial
stream ranges from 50 MHz to 700 MHz ( 50 MHz *28 bits =
1.4 Gbps / 2 = 700 MHz ).
Ser — Spread Spectrum Compatibility
The RxCLKIN of the Channel Link input is capable of tracking
spread spectrum clocking (SSC) from a host source. The Rx-
CLKIN will accept spread spectrum tracking up to 35kHz
modulation and ±0.5, ±1 or ±2% deviations (center spread).
The maximum conditions for the RxCLKIN input are: a mod-
ulation frequency of 35kHz and amplitude deviations of ±2%
(4% total).
SER — INTEGRATED SIGNAL CONDITIONING
FEATURES
Ser — VOD Select (VODSEL)
The DS92LV0411 differential output voltage may be in-
creased by setting the VODSEL pin High. When VODSEL is
Low, the DC VOD is at the standard (default) level. When
VODSEL is High, the DC VOD is increased in level. The in-
creased VOD is useful in extremely high noise environments
and also on extra long cable length applications. When using
de-emphasis it is recommended to set VODSEL = H to avoid
excessive signal attenuation especially with the larger de-
emphasis settings. This feature may be controlled by the
external pin or by register.
Ser — De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis be-
ginning one full bit time after a logic transition that the device
drives. This is useful to counteract loading effects of long or
lossy cables. This pin should be left open for standard switch-
ing currents (no de-emphasis) or if controlled by register. De-
emphasis is selected by connecting a resistor on this pin to
ground, with R value between 0.5 kΩ to 1 MΩ, or by register
setting. When using De-Emphasis it is recommended to set
VODSEL = H.
VODSEL
TABLE 3. Ser — Differential Output Voltage
Input
H
L
±450
±300
VOD
mV
Effect
mVp-p
VOD
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900
600