ATTINY461V-10PU Atmel, ATTINY461V-10PU Datasheet - Page 31

• Manufacturer Part Number: ATTINY461V-10PU
• Description: Microcontrollers (MCU) 4kB Flash 0.256kB EEPROM 16 I/O Pins
• Manufacturer: Atmel

Specifications of ATTINY461V-10PU

• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Package / Case: PDIP-20
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• Ram Size: 256 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.7
6.3
6.3.1
2588E–AVR–08/10
System Clock Prescaler
Default Clock Source
Switching Time
Table 6-12.
Notes:
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal Oscillator running at 8 MHz with longest start-up
time and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or High-voltage Programmer.
For low-voltage devices (ATtiny261V/461V/861V) it should be noted that unprogramming the
CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for
maximum 4 MHz operation (see
internal oscillator directly to the system clock line will run the device at 8 MHz.
The ATtiny261/461/861 system clock can be divided by setting the
Register” on page
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
and clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
CKSEL0
0
1
1
1
1
FLASH
1. These options should only be used when not operating close to the maximum frequency of the
2. These options are intended for use with ceramic resonators and will ensure frequency stability
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
are divided by a factor as shown in
SUT1:0
Start-up Times for the Crystal Oscillator Clock Selection (Continued)
00
01
10
11
11
32. This feature can be used to decrease power consumption when the
Start-up Time from
Power-down and
16K (16384) CK
16K (16384) CK
16K (16384) CK
1K (1024)CK
1K (1024)CK
Power-save
Section 19.3 on page
(2)
(2)
Table 6-13 on page
Additional Delay
14CK + 64 ms
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
(V
from Reset
188), but routing the clock signal from the
CC
14CK
= 5.0V)
34.
“CLKPR – Clock Prescale
Recommended Usage
Ceramic resonator,
fast rising power
Ceramic resonator,
slowly rising power
Crystal Oscillator,
BOD enabled
Crystal Oscillator,
fast rising power
Crystal Oscillator,
slowly rising power
I/O
, clk
ADC
, clk
CPU
31
,