A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 115

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User Pins
Name
GPIO_x
IO
In/out
In/out
Type
Polarity/Bus Size
32
Microcontroller Subsystem (MSS)
General Purpose I/O (GPIO).
The MSS GPIO pin functions as an input, output, tristate, or bidirectional
buffer with configurable interrupt generation and Schmitt trigger support.
Input and output signal levels are compatible with the I/O standard selected.
Unused GPIO pins are tristated and do not include pull-up or pull-down
resistors.
During power-up, the used GPIO pins are tristated with no pull-up or
pull-down resistors until Sys boot configures them.
Some of these pins are also multiplexed with integrated peripherals in the
MSS (SPI, I
GPIOs can be routed to dedicated I/O buffers (MSSIOBUF) or in some
cases to the FPGA fabric interface through an IOMUX. This allows GPIO
pins to be multiplexed as either I/Os for the FPGA fabric, the ARM
Cortex™-M3 or for given integrated MSS peripherals. The MSS peripherals
are not multiplexed with each other; they are multiplexed only with the GPIO
block. For more information, see the General Purpose I/O Block (GPIO)
section in the
FPGA user I/O
The FPGA user I/O pin functions as an input, output, tristate or bidirectional
buffer. Input and output signal levels are compatible with the I/O standard
selected. Unused I/O pins are disabled by Libero IDE software and include a
weak pull-up resistor. During power-up, the used I/O pins are tristated with
no pull-up or pull-down resistors until I/O enable (there is a delay after
voltage stabilizes, and different I/O banks power up sequentially to avoid a
surge of ICCI).
Some of these pins are also multiplexed with integrated peripherals in the
MSS (Ethernet MAC and external memory controller).
During programming, I/Os become tristated and weakly pulled up to VCCI.
With the VCCI and VCC supplies continuously powered up, when the device
transitions from programming to operating mode, the I/Os are instantly
configured to the desired user configuration. For more information, see the
SmartFusion FPGA User I/Os section in the
User’s
The naming convention used for each FPGA user I/O is:
IOuxwByVz where:
u = I/O pair number in bank, starting at 00 from the northwest I/O bank and
incrementing clockwise.
x = P (positive) or N (negative) or S (single-ended) or R (regular, single-
ended).
w = D (differential pair) or P (pair) or S (single-ended) or R (regular, single-
ended).
y = Bank number starting at 0 from northwest I/O bank and incrementing
clockwise.
z = V
REF
Guide.
mini bank number.
2
C, and UART).
SmartFusion Microcontroller Subsystem User’s
R e v i s i o n 6
SmartFusion Intelligent Mixed Signal FPGAs
Description
SmartFusion FPGA Fabric
Guide.
5 -5
®