A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 51

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-58 • Minimum and Maximum DC Input and Output Levels
Figure 2-10 • AC Loading
Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-60 • 3.3 V PCI
Table 2-61 • 3.3 V PCI-X
3.3 V PCI/PCI-X
Drive Strength
Per PCI specification
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
0
*
Speed Grade
Std.
–1
Note:
Speed Grade
Std.
–1
Note:
Measuring point = V
Test Point
Datapath
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Worst Commercial-Case Conditions: T
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Worst Commercial-Case Conditions: T
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; SoC Products Group loadings
for enable path characterization are described in
AC loadings are defined per PCI/PCI-X specifications for the datapath; SoC Products Group loading for
tristate is described in
Timing Characteristics
R = 25
t
t
Input High (V)
DOUT
0.60
0.50
DOUT
0.60
0.50
trip.
3.3
Min.
See
V
2.54
2.54
2.11
2.11
R to VCCXXXXIOBX for t
t
t
R to GND for t
DP
DP
VIL
Table 2-21 on page 2-24
Max.
V
0.04
0.03
0.04
0.03
Table
t
t
DIN
DIN
0.285 * VCCxxxxIOBx for t
0.615 * VCCxxxxIOBx for t
DP
2-59.
Min.
Measuring Point* (V)
(R)
V
0.82
0.68
0.77
0.64
t
t
PY
PY
VIH
Max.
DP
t
t
V
0.39
0.32
0.39
0.32
EOUT
EOUT
(F)
J
J
Enable Path
= 85°C, Worst-Case VCC = 1.425 V,
= 85°C, Worst-Case VCC = 1.425 V,
for a complete table of trip points.
Test Point
Per PCI curves
R e v i s i o n 6
Max.
VOL
2.58
2.15
2.58
2.15
V
t
t
ZL
ZL
Figure
R = 1 k
DP(R)
DP(F)
VOH
Min.
1.88
1.57
1.88
1.57
V
2-10.
t
t
ZH
ZH
SmartFusion Intelligent Mixed Signal FPGAs
Table 2-7 on page 2-9
Table 2-7 on page 2-9
mA mA
I
OL
10 pF for t
R to VCCXXXXIOBX for t
R to GND for t
5 pF for t
3.06
2.55
3.06
2.55
t
t
V
LZ
LZ
I
REF
OH
(typ.) (V)
–
HZ
ZH
3.39
2.82
3.39
2.82
t
t
Max.
mA
HZ
HZ
I
/ t
OSL
/ t
HZ
LZ
ZHS
1
/ t
/ t
ZH
4.64
3.87
4.64
3.87
t
t
ZL
ZLS
ZLS
/ t
for derating values.
for derating values.
/ t
ZHS
ZLS
Max.
I
mA
LZ
OSH
/ t
C
t
3.94
3.28
t
3.94
3.28
1
ZL
LOAD
ZHS
ZHS
/ t
10
ZLS
µA
15
I
(pF)
IL
Units
Units
2
ns
ns
ns
ns
µA
2- 39
I
15
IH
2