A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 60

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Figure 2-16 • Input Register Timing Diagram
Table 2-70 • Input Data Register Propagation Delays
2- 48
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
Data
Preset
Clear
Out_1
CLK
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For the derating values at specific junction temperature and voltage supply levels, refer to
for derating values.
Worst Commercial-Case Conditions: T
Input Register
Timing Characteristics
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
50%
50%
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
t
ICLKQ
IHD
50%
50%
50%
Description
t
IWPRE
t
IPRE2Q
50%
J
50%
= 85°C, Worst-Case VCC = 1.425 V
t
R e visio n 6
IRECPRE
50%
t
ICLR2Q
50%
t
IWCLR
50%
50%
50%
t
IRECCLR
50%
t
ICKMPWH
t
IREMPRE
50%
Table 2-7 on page 2-9
0.38 0.45
0.00 0.00
0.00 0.00
0.22 0.22
0.22 0.22
0.24 0.29
0.27 0.32
0.00 0.00
0.00 0.00
0.46 0.55
0.46 0.55
0.23 0.27
0.23 0.27
0.36 0.36
0.32 0.32
50%
t
–1
ICKMPWL
Std.
50%
t
50%
IREMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns