NAND512W3A2SN6E NUMONYX, NAND512W3A2SN6E Datasheet - Page 15

• Manufacturer Part Number: NAND512W3A2SN6E
• Description: IC FLASH 512MBUT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND512W3A2SN6E

• Format - Memory: FLASH
• Memory Type: FLASH - NAND
• Memory Size: 512M (64M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Numonyx SLC SP 70 nm
4
4.1
4.2
4.3
4.4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see
Command input
Command input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See
Address input
Address input bus operations are used to input the memory address. Four bus cycles are
required to input the addresses for the 512 Mbit devices (refer to
Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See
Data input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See
Data output
Data Output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See
Figure 18
Figure 19
Figure
Figure 21
20,
and
and
and
Table
Table 6: Bus
Table 21
Table 21
Table 22
21, and
for details of the timings requirements.
for details of the timings requirements.
for details of the timings requirements.
Table 22
operations, for a summary.
210403 - Rev 2
for details of the timings requirements.
Table 7
and
Bus operations
Table
8,
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