DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 15

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

2.4 LED INTERFACE
The DP83848VYB supports three configurable Light Emitting
Diode (LED) pins. The device supports three LED configura-
tions: Link, Speed, Activity and Collision. Function are multi-
The LED_LINK pin in Mode 1 indicates the link status of the
port. In 100BASE-T mode, link is established as a result of
input receive amplitude compliant with the TP-PMD specifi-
cations which will result in internal generation of signal detect.
A 10 Mb/s Link is established as a result of the reception of
at least seven consecutive normal Link Pulses or the recep-
tion of a valid 10BASE-T packet. This will cause the assertion
of LED_LINK. LED_LINK will deassert in accordance with the
Link Loss Timer as specified in the IEEE 802.3 specification.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
present.
The LED_LINK pin in Mode 2 and Mode 3 will be ON to indi-
cate Link is good and BLINK to indicate activity is present on
activity.
The LED_SPEED pin indicates 10 or 100 Mb/s data rate of
the port. The LED is ON when operating in 100Mb/s mode
and OFF when operating in 10 Mb/s mode. The functionality
of this LED is independent of mode selected.
The LED_ACT/COL pin in Mode 1 indicates the presence of
either transmit or receive activity. The LED will be ON for Ac-
tivity and OFF for No Activity. In Mode 2, this pin indicates the
Collision status of the port. The LED will be ON for Collision
and OFF for No Collision.
The LED_ACT/COL pin in Mode 3 indicates Duplex status for
10 Mb/s or 100 Mb/s operation. The LED will be ON for Full
Duplex and OFF for Half Duplex.
Mode
1
2
3
LED_CFG[1]
don't care
(bit 6)
0
1
LED_CFG[0] (bit 5)
or (pin 40)
1
0
0
FIGURE 1. PHYAD Strapping Example
TABLE 3. LED Mode Selection
ON for Good Link
OFF for No Link
ON for Good Link
BLINK for Activity
ON for Good Link
BLINK for Activity
LED_LINK
15
plexed among the LEDs. The PHY Control Register (PHYCR)
for the LEDs can also be selected through address 19h, bits
[6:5].
See Table 3 for LED Mode selection.
In 10 Mb/s half duplex mode, the collision LED is based on
the COL signal.
Since these LED pins are also used as strap options, the po-
larity of the LED is dependent on whether the pin is pulled up
or down.
2.4.1 LEDs
Since the Auto-Negotiation (AN) strap options share the LED
output pins, the external components required for strapping
and LED usage must be considered in order to avoid con-
tention.
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent on
the logic level sampled by the corresponding AN input upon
power-up/reset. For example, if a given AN input is resistively
pulled low then the corresponding output will be configured
as an active high driver. Conversely, if a given AN input is
resistively pulled high, then the corresponding output will be
configured as an active low driver.
Refer to Figure 2 for an example of AN connections to external
components. In this example, the AN strapping results in Au-
to-Negotiation disabled with 10/100 Half/Full-Duplex adver-
tised .
The adaptive nature of the LED outputs helps to simplify po-
tential implementation issues of these dual purpose pins.
ON in 100 Mb/s
OFF in 10 Mb/s
ON in 100 Mb/s
OFF in 10 Mb/s
ON in 100 Mb/s
OFF in 10 Mb/s
LED_SPEED
30011702
ON for Activity
OFF for No Activity
ON for Collision
OFF for No Collision
ON for Full Duplex
OFF for Half Duplex
LED_ACT/LED_COL
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