DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 4

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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5.0 Design Guidelines ......................................................................................................................... 28
6.0 Reset Operation ............................................................................................................................ 32
7.0 Register Block ............................................................................................................................... 33
Absolute Maximum Ratings .................................................................................................................. 55
8.0 AC and DC Specifications ............................................................................................................... 55
4.3 10BASE-T TRANSCEIVER MODULE ............................................................................................ 25
5.1 TPI NETWORK CIRCUIT ............................................................................................................. 28
5.2 ESD PROTECTION ..................................................................................................................... 28
5.3 CLOCK IN (X1) REQUIREMENTS ................................................................................................. 28
5.4 POWER FEEDBACK CIRCUIT ..................................................................................................... 29
5.5 POWER DOWN/INTERRUPT ....................................................................................................... 30
5.6 ENERGY DETECT MODE ............................................................................................................ 30
5.7 THERMAL Vias RECOMMENDATION ........................................................................................... 30
6.1 HARDWARE RESET ................................................................................................................... 32
6.2 SOFTWARE RESET .................................................................................................................... 32
7.1 REGISTER DEFINITION .............................................................................................................. 36
7.2 EXTENDED REGISTERS ............................................................................................................. 43
8.1 DC SPECIFICATIONS ................................................................................................................. 55
8.2 AC SPECIFICATIONS ................................................................................................................. 57
4.2.10 100BASE-TX Link Integrity Monitor .......................................................................................... 25
4.2.11 Bad SSD Detection ............................................................................................................... 25
4.3.1 Operational Modes .................................................................................................................. 25
4.3.2 Smart Squelch ........................................................................................................................ 26
4.3.3 Collision Detection and SQE .................................................................................................... 26
4.3.4 Carrier Sense ......................................................................................................................... 26
4.3.5 Normal Link Pulse Detection/Generation .................................................................................... 26
4.3.6 Jabber Function ...................................................................................................................... 26
4.3.7 Automatic Link Polarity Detection and Correction ........................................................................ 27
4.3.8 Transmit and Receive Filtering ................................................................................................. 27
4.3.9 Transmitter ............................................................................................................................ 27
4.3.10 Receiver .............................................................................................................................. 27
5.5.1 Power Down Control Mode ...................................................................................................... 30
5.5.2 Interrupt Mechanisms .............................................................................................................. 30
7.1.1 Basic Mode Control Register (BMCR) ........................................................................................ 37
7.1.2 Basic Mode Status Register (BMSR) ......................................................................................... 38
7.1.3 PHY Identifier Register #1 (PHYIDR1) ....................................................................................... 39
7.1.4 PHY Identifier Register #2 (PHYIDR2) ....................................................................................... 39
7.1.5 Auto-Negotiation Advertisement Register (ANAR) ....................................................................... 39
7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) .......................................... 40
7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) ........................................... 41
7.1.8 Auto-Negotiate Expansion Register (ANER) ............................................................................... 42
7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) ........................................................... 42
7.2.1 PHY Status Register (PHYSTS) ............................................................................................... 43
7.2.2 MII Interrupt Control Register (MICR) ........................................................................................ 45
7.2.3 MII Interrupt Status and Misc. Control Register (MISR) ................................................................ 46
7.2.4 False Carrier Sense Counter Register (FCSCR) .......................................................................... 47
7.2.5 Receiver Error Counter Register (RECR) ................................................................................... 47
7.2.6 100 Mb/s PCS Configuration and Status Register (PCSR) ............................................................ 48
7.2.7 RMII and Bypass Register (RBR) .............................................................................................. 48
7.2.8 LED Direct Control Register (LEDCR) ........................................................................................ 49
7.2.9 PHY Control Register (PHYCR) ................................................................................................ 49
7.2.10 10 Base-T Status/Control Register (10BTSCR) ......................................................................... 51
7.2.11 CD Test and BIST Extensions Register (CDCTRL1) .................................................................. 53
7.2.12 Energy Detect Control (EDCR) ............................................................................................... 53
8.2.1 Power Up Timing .................................................................................................................... 57
8.2.2 Reset Timing ......................................................................................................................... 58
8.2.3 MII Serial Management Timing ................................................................................................ 59
8.2.4 100 Mb/s MII Transmit Timing .................................................................................................. 59
8.2.5 100 Mb/s MII Receive Timing ................................................................................................... 60
8.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing ............................................ 60
8.2.7 100BASE-TX Transmit Packet Deassertion Timing ..................................................................... 61
8.2.8 100BASE-TX Transmit Timing (t
8.2.9 100BASE-TX Receive Packet Latency Timing ............................................................................ 62
8.2.10 100BASE-TX Receive Packet Deassertion Timing .................................................................... 62
8.2.11 10 Mb/s MII Transmit Timing .................................................................................................. 63
8.2.12 10 Mb/s MII Receive Timing ................................................................................................... 63
R/F
& Jitter) ................................................................................ 61
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