DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 39

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

15:10
15:0
Bit
9:4
3:0
Bit
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848VYB. The Identifier consists of a con-
catenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may
return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network
management. National's IEEE assigned OUI is 080017h.
7.1.3 PHY Identifier Register #1 (PHYIDR1)
7.1.4 PHY Identifier Register #2 (PHYIDR2)
7.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation.
Bit
15
14
13
12
11
VNDR_MDL
OUI_MSB
Bit Name
MDL_REV
Bit Name
OUI_LSB
RESERVED
RESERVED
ASM_DIR
Bit Name
NP
RF
TABLE 16. Negotiation Advertisement Register (ANAR), address 0x04h
<0101 11>, RO/P OUI Least Significant Bits:
<00 1010>, RO/P Vendor Model Number:
<0010 0000 0000
<0010>, RO/P
TABLE 14. PHY Identifier Register #1 (PHYIDR1), address 0x02h
TABLE 15. PHY Identifier Register #2 (PHYIDR2), address 0x03h
0000>, RO/P
Default
Default
0, RO/P
Default
0, RW
0, RW
0, RW
0, RW
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register
respectively.
The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit
to bit 9).
Model Revision Number:
Four bits of the vendor model revision number are mapped from bits 3 to 0 (most
significant bit to bit 3). This field will be incremented for all major device changes.
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored in bits 15
to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE
standard refers to these as bits 1 and 2).
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
RESERVED by IEEE: Writes ignored, Read as 0.
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
RESERVED for Future IEEE use: Write as 0, Read as 0
Asymmetric PAUSE Support for Full Duplex Links:
The ASM_DIR bit indicates that asymmetric PAUSE is supported.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B,
Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in
PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the optional MAC
control sublayer and the pause function as specified in clause 31 and annex 31B
of 802.3u.
0= No MAC based full duplex flow control.
39
Description
Description
Description
www.national.com