DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 28

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.0 Functional Description
3.12.3 MII Serial Management Access
Management
Management Data Clock (MDC) and Management Data
Input/Output (MDIO). MDC has a maximum clock rate of 25
MHz and no minimum rate. The MDIO line is bi-directional
and may be shared by up to 32 devices. The internal PHY
counts as one of these 32 devices.
The internal PHY has the advantage of having direct
register access but can also be controlled exactly like a
PHY, with a default address of 1Fh, connected to the MII.
Access and control of the MDC and MDIO pins is done via
the MII/EEPROM Access Register (MEAR). The clock
(MDC) is created by alternating writes of 0 then 1 to the
MDC bit (bit 6). Control of data direction is done by the
MDDIR bit (bit 5). Data is either recorded or written by the
MDIO bit (bit 4). Setting the MDDIR bit to a 1 allows the
DP83816 to drive the MDIO pin. Setting the MDDIR bit to a
0 allows the MDIO bit to reflect the value of the MDIO pin.
See Section 4.2.3
This bit-bang access of the MDC and MDIO pins thus
requires 64 accesses to the MEAR register to complete a
single PHY register transaction. Since a PHY device is
typically
management
initialization time and therefore is not time critical.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid
contention during a read transaction, no device shall
actively drive the MDIO signal during the first bit of
For write transactions, the DP83816 writes data to the
addressed PHY thus eliminating the requirement for MDIO
Turnaround. The Turnaround time is filled by the DP83816
by
relationship for a typical MII register write access.
Read Operation
Write Operation
MII Management
MDIO
MDIO
MDC
Serial Protocol
(STA)
(PHY)
inserting
self
Z
Idle
Z
access
access
0
<10>.
configuring
Start
1 1
Opcode
(Read)
Figure 3-16
to
0 0
is
the
usually
(PHYAD = 0Ch)
and
PHY Address
1 1 0 0 0 0 0 0 0
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
PHY(s)
Figure 3-15 Typical MDC/MDIO Read Operation
adaptive
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
shows
(Continued)
only
Table 3-2 Typical MDIO Frame Format
is
Register Address
(00h = BMCR)
required
the
this
done
timing
serial
via
Z
Z
at
Z
28
TA
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
3.12.4 Serial Management Access Protocol
The serial control interface clock (MDC) has a maximum
clock rate of 25 MHz and no minimum rate. The MDIO line
is bi-directional and may be shared by up to 32 devices.
The MDIO frame format is shown in Table 3-2.
If external PHY devices may be attached and removed
from the MII there should be a 15 KΩ pull-down resistor on
the MDIO signal. If the PHY will always be connected then
there should be a 1.5 kΩ pull-up resistor which, during
IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the DP83816 sends a
sequence of 32 contiguous logic ones on MDIO provides
the PHY(s) with a sequence that can be used to establish
synchronization. This preamble may be generated either
by driving MDIO high for 32 consecutive MDC clock cycles,
or by simply allowing the MDIO pull-up resistor to pull the
MDIO pin high during which time 32 MDC clock cycles are
provided. In addition 32 MDC clock cycles should be used
to re-sync the device if an invalid start, opcode, or
turnaround bit is detected.
Turnaround. The addressed PHY drives the MDIO with a
zero for the second bit of turnaround and follows this with
the
relationship
driven/received by the DP83816 and a PHY for a typical
register read access.
3.12.5 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface include
separate dedicated receive and transmit busses. These
two data buses, along with various control and indication
signals, allow for the simultaneous exchange of data
between the DP83816 and PHY(s).
required
between
data.
Register Data
Figure 3-15
MDC
and
shows
the
www.national.com
the
MDIO
Z
Idle
Z
timing
as