DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 80

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.0 Buffer Management
5.1.3 Multiple Descriptor Packets
A single packet may also cross descriptor boundaries. This
is indicated by setting the MORE bit in all descriptors
except the last one in the packet. Ethernet applications
(bridges, switches, routers, etc.) can optimize memory
utilization by using a single small buffer per receive
descriptor, and allowing the DP83816 hardware to use the
minimum number of buffers necessary to store an
incoming packet.
addr 10100
addr 10100
10140
10140
MAC hdr
1
link
ptr
Figure 5-3 List and Ring Descriptor Organization
(Continued)
14
Figure 5-2 Multiple Descriptor Packets
multiple descriptor / single fragment
Descriptors Organized in a Ring
addr 10140
Descriptors Organized in a Linked List
addr 10140
10180
10180
netwk hdr
1
link
ptr
80
20
5.1.4 Descriptor Lists
Descriptors are organized in linked lists using the link field.
The system designer may also choose to implement a
"ring" of descriptors by linking the last descriptor in the list
back to the first. A list of descriptors may represent any
number of packets or packet fragments.
addr 10180
addr 10180
101C0
101C0
0
data
link
ptr
addr 101C0
addr 101C0
30
10100
00000
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