DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 68

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.3.3 PHY Identifier Register #1
The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this device. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model
revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY
Identifier is intended to support network management. National Semiconductor's IEEE assigned OUI is 080017h.
4.3.4 PHY Identifier Register #2
4.3.5 Auto-Negotiation Advertisement Register
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-
Negotiation.
15:10
12:11
15:0
Bit
Bit
Bit
9:4
3:0
15
14
13
10
VNDR_MDL
Bit Name
Bit Name
Bit Name
MDL_REV
OUI_MSB
OUI_LSB
Reserved
Reserved
PAUSE
NP
RF
Offset: 0088h
Offset: 008Ch
Offset: 0090h
(Continued)
Tag: PHYIDR1
Tag: PHYIDR2
Tag: ANAR
OUI Most Significant Bits: Default: <0010 0000 0000 0000>
Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most significant two bits of
the OUI are ignored (the IEEE standard refers to these as bits 1 and 2).
OUI Least Significant Bits: Default: <01 0111>
Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of this register respectively.
Vendor Model Number: Default: <00 0010>
The six bits of vendor model number are mapped to bits 9 to 4 (most significant bit to bit 9).
Model Revision Number: Default: <0001>
Four bits of the vendor model revision number are mapped to bits 3 to 0 (most significant bit to bit 3). This
field will be incremented for all major device changes.
Next Page Indication: Default: 0
0 = Next Page Transfer not desired
1 = Next Page Transfer desired
Reserved by IEEE: Writes ignored, Read as 0
Remote Fault: Default: 0
1 = Advertises that this device has detected a Remote Fault
0 = No Remote Fault detected
Reserved for Future IEEE use: Write as 0, Read as 0
PAUSE: Default: dependent on the setting of the PAUSE_ADV in the CFG register
1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause
function as specified in clause 31 and annex 31B of 802.3u.
0 = No MAC based full duplex flow control
Access: Read Only
Access: Read Only
Access: Read Write
Size: 16 bits
Size: 16 bits
Size: 16 bits
68
Description
Description
Description
Hard Reset: 2000h
Hard Reset: 5C21h
Hard Reset: 05E1h
www.national.com