DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 77

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.0 Buffer Management
The buffer management scheme used on the DP83816
allows quick, simple and efficient use of the frame buffer
memory. Frames are saved in similar formats for both
transmit and receive. The buffer management scheme also
uses
information. This allows effective transfers of data from the
receive buffer to the transmit buffer by simply transferring
the descriptor from the receive queue to the transmit
queue.
The format of the descriptors allows the packets to be
saved in a number of configurations. A packet can be
stored in memory with a single descriptor and a single
packet fragment, or multiple descriptors each with a single
fragment. This flexibility allows the user to configure the
DP83816 to maximize efficiency. Architecture of the
specific system’s buffer memory, as well as the nature of
network
configuration of packet descriptors and fragments.
The original DP83810A Descriptor format supported
multiple fragments per descriptor. DP83816 only supports
a single fragment per descriptor. By default, DP83816 will
use the descriptor format shown above. By setting
CFG:EUPHCOMP, software may force compatibility with
the previous DP83810A Descriptor format (although still
Bit
31
30
29
28
separate
Offset
0000h
0004h
0008h
traffic,
SUPCRC
INCCRC
MORE
OWN
INTR
buffers
Tag
will
cmdsts
bufptr
Tag
link
determine
and
Descriptor Ownership
More descriptors
Interrupt
Suppress CRC /
Include CRC
32-bit "link" field to the next descriptor in the linked list. Bits 1-0 must be 0, as
descriptors must be aligned on 32-bit boundaries.
32-bit Command/Status Field (bit-encoded).
32-bit pointer to the first fragment or buffer. In transmit descriptors, the buffer can
begin on any byte boundary. In receive descriptors, the buffer must be aligned on a
32-bit boundary.
descriptors
Description
Table 5-2 cmdsts Common Bit Definitions
the
Table 5-1 DP83816 Descriptor Format
most
for
suitable
packet
Set to 1 by the data producer of the descriptor to transfer
ownership to the data consumer of the descriptor. Set to 0 by the
data consumer of the descriptor to return ownership to the data
producer of the descriptor. For transmit descriptors, the driver is
the data producer, and the DP83816 is the data consumer. For
receive descriptors, the DP83816 is the data producer, and the
driver is the data consumer.
Set to 1 to indicate that this is NOT the last descriptor in a packet
(there are MORE to follow). When 0, this descriptor is the last
descriptor in a packet. Completion status bits are only valid when
this bit is zero.
Set to 1 by software to request a “descriptor interrupt" when
DP83816 transfers the ownership of this descriptor back to
software.
In transmit descriptors, this indicates that CRC should not be
appended by the MAC. On receives, this bit is always set, as the
CRC is always copied to the end of the buffer by the hardware.
77
5.1 Overview
The buffer management design has the following goals:
— simplicity,
— efficient use of the PCI bus (the overhead of the buffer
— low CPU utilization,
— flexibility.
Descriptors may be either per-packet or per-packet-
fragment. Each descriptor may describe one packet
fragment.
symmetrical.
5.1.1 Descriptor Format
DP83816 uses a symmetrical format for transmit and
receive descriptors. In bridging and switching applications
this symmetry allows software to forward packets by simply
moving the list of descriptors that describe a single
received packet from the receive list of one MAC to the
transmit list of another. Descriptors must be aligned on an
even long word (32-bit) boundary.
only single fragment descriptors are supported). When
CFG:EUPHCOMP is set, then bufptr is at offset 0Ch, and
the 32-bit bufcnt field at offset 08h is ignored.
Some of the bit definitions in the cmdsts field are common
to both receive and transmit descriptors:
management technique is minimal),
Description
Receive
Usage
and
transmit
descriptors
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