PIC18F4455-I/ML Microchip Technology, PIC18F4455-I/ML Datasheet - Page 100

• Manufacturer Part Number: PIC18F4455-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4455-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

PIC18F2455/2550/4455/4550
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1:
EXAMPLE 8-3:
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39632E-page 98
RES3:RES0
;
;
;
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
=
=
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
WREG
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
WREG
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2
(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L)
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
8
8
16
) +
) +
) +
EQUATION 8-2:
EXAMPLE 8-4:
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
;
;
;
;
;
SIGN_ARG1
;
CONT_CODE
:
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB RES3
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB RES3
= (ARG1H • ARG2H • 2
(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L,W
ARG2H
PRODL, W
RES1, F
PRODH, W
WREG
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
WREG
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
16 x 16 SIGNED
MULTIPLY ROUTINE
© 2009 Microchip Technology Inc.
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
; ARG1H:ARG1L neg?
; no, done
;
;
;
8
8
16
) +
) +
) +
16
16
) +
)