PIC18F4455-I/ML Microchip Technology, PIC18F4455-I/ML Datasheet - Page 276

• Manufacturer Part Number: PIC18F4455-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4455-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

PIC18F2455/2550/4455/4550
21.8
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
TABLE 21-2:
DS39632E-page 274
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(4)
2:
3:
4:
(4)
Use of the CCP2 Trigger
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers and/or bits are not implemented on 28-pin devices.
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
SPPIE
SPPIP
SPPIF
RDPU
OSCFIF
OSCFIE
OSCFIP
TRISB7
LATB7
ADFM
Bit 7
RB7
—
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(4)
(4)
(4)
(4)
TRISA6
TRISB6
RA6
LATB6
CMIE
CMIP
CMIF
ADIF
ADIE
ADIP
Bit 6
RB6
—
—
—
—
—
—
(2)
(2)
TRISA5
TRISB5
VCFG1
ACQT2
USBIF
USBIE
USBIP
LATB5
CHS3
RCIF
RCIE
RCIP
Bit 5
RA5
RB5
—
—
—
TRISA4
TRISB4
VCFG0
ACQT1
INT0IE
LATB4
CHS2
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
TXIF
RA4
RB4
—
—
—
RE3
TRISA3
TRISB3
PCFG3
ACQT0
LATB3
SSPIF
SSPIE
SSPIP
BCLIE
BCLIP
BCLIF
CHS1
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
RBIE
Bit 3
RA3
RB3
ACQ
—
—
(1,3)
time selected before the Special Event Trigger
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
TRISA2
TRISB2
TRISE2
PCFG2
ADCS2
LATB2
RE2
LATE2
CHS0
Bit 2
RA2
RB2
(4)
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISA1
TRISB1
TRISE1
PCFG1
ADCS1
INT0IF
LATB1
RE1
LATE1
Bit 1
© 2009 Microchip Technology Inc.
RA1
RB1
(4)
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISA0
TRISB0
TRISE0
PCFG0
ADCS0
ADON
LATB0
RE0
LATE0
RBIF
Bit 0
RA0
RB0
(4)
on page
Values
Reset
53
56
56
56
56
56
56
54
54
54
54
54
56
56
56
56
56
56
56
56