PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet - Page 266

• Manufacturer Part Number: PIC18LF8490-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8490-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F6390/6490/8390/8490
22.6
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Table 22-2 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
22.7
The rate at which the COM and SEG outputs changes
is called the LCD frame frequency
TABLE 22-4:
TABLE 22-5:
DS39629C-page 264
Multiplex
LP3:LP0
Note:
Static
1/2
1/3
1/4
1
2
3
4
5
6
7
Pixel Control
LCD Frame Frequency
Clock source is (F
Timer1 Osc/32 or INTRC/32.
Clock Source/(4 x 1 x (LP3:LP0 + 1))
Clock Source/(2 x 2 x (LP3:LP0 + 1))
Clock Source/(1 x 3 x (LP3:LP0 + 1))
Clock Source/(1 x 4 x (LP3:LP0 + 1))
Static
125
83
62
50
42
36
31
FRAME FREQUENCY
FORMULAS
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
F
TIMER1 @ 32.768 kHz OR
INTRC OSCILLATOR
OSC
Frame Frequency =
@ 32 MHz,
125
1/2
83
62
50
42
36
31
OSC
/4)/8192,
167
111
1/3
83
67
56
48
42
125
1/4
83
62
50
42
36
31
22.8
LCD waveform generation is based on the philosophy
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC com-
ponent and it can take only one of the two rms values.
The higher rms value will create a dark pixel and a
lower rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 V
over a single frame, whereas Type-B waveform takes
two frames.
Figure 22-4 through Figure 22-14 provide waveforms
for
quarter-multiplex drives for Type-A and Type-B
waveforms.
Note 1: If Sleep has to be executed with LCD
static, half-multiplex, one-third-multiplex and
2: When
LCD Waveform Generation
Sleep enabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when V
‘0’.
(F
irrespective of the LCDCON<SLPEN>
setting, the LCD goes into Sleep. Thus,
take care to see that V
when Sleep is executed.
OSC
/4)/8192, if Sleep is executed
the
© 2007 Microchip Technology Inc.
LCD
DC
DC
clock
on all the pixels is
on all pixels is ‘0’
source
DC
is